April 2006 - coreboot - mail.coreboot.org

[LinuxBIOS] Tyan S2881 build tutorial online
by Ward Vandewege April 27, 2006

April 27, 2006

Hi all, As promised, I've just uploaded a Tyan S2881 build tutorial to the wiki: http://wiki.linuxbios.org/index.php/Tyan_S2881_Build_Tutorial We (the FSF) hope this will help others to get LinuxBIOS going. A _very big_ thank you to all of you, and in particular Yinghai, Ron, Stefan, Richard and Alan for all your help to get me to the point where we have a working LinuxBIOS machine. We will be deploying 2 or 3 of these GX28 boxes shortly. Soon, all @(lists.)gnu.org and @fsf.org e-mail will be processed by machines running LinuxBIOS! As you will see in the wiki page, there is still one thing that I have not gotten to work - VGA output. It's not a big issue for us, but I'd like to get it working nevertheless, if only to complete the build tutorial. I'll be posting about that shortly, I'm sure :) Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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[LinuxBIOS] Want to know whether linuxbios works on my PC
by Zhen Xu April 27, 2006

April 27, 2006

Hi, all, I'm interested in linuxbios and planning to do some experiments with it. However, I don't know whether linuxbios works on my PC. It's a IBM thinkcentre 8114, chip set is Intel 945G and the result of 'listpci -vvv' is as below: 00:00.0 Host bridge: Intel Corp.: Unknown device 2770 (rev 02) Subsystem: IBM: Unknown device 02f6 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- Latency: 0 Capabilities: [e0] #09 [5109] 00:02.0 VGA compatible controller: Intel Corp.: Unknown device 2772 (rev 02) (prog-if 00 [VGA]) Subsystem: IBM: Unknown device 02f6 Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 5 Region 0: Memory at d0100000 (32-bit, non-prefetchable) [size=512K] Region 1: I/O ports at 30c0 [size=8] Region 2: Memory at c0000000 (32-bit, prefetchable) [size=256M] Region 3: Memory at d0180000 (32-bit, non-prefetchable) [size=256K] Capabilities: [90] Message Signalled Interrupts: 64bit- Queue=0/0 Enable- Address: 00000000 Data: 0000 Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:02.1 Display controller: Intel Corp.: Unknown device 2776 (rev 02) Subsystem: IBM: Unknown device 02f6 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at 20000000 (32-bit, non-prefetchable) [disabled] [size=512K] Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:1b.0 Class 0403: Intel Corp.: Unknown device 27d8 (rev 01) Subsystem: IBM: Unknown device 02f6 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, cache line size 08 Interrupt: pin A routed to IRQ 9 Region 0: Memory at d01c0000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [60] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [70] #10 [0091] 00:1c.0 PCI bridge: Intel Corp.: Unknown device 27d0 (rev 01) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, cache line size 08 Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00004000-00004fff Memory behind bridge: d0000000-d00fffff Prefetchable memory behind bridge: 00000000fff00000-0000000000000000 BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [40] #10 [0141] Capabilities: [80] Message Signalled Interrupts: 64bit- Queue=0/0 Enable- Address: 00000000 Data: 0000 Capabilities: [90] #0d [0000] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable+ DSel=0 DScale=0 PME- 00:1c.1 PCI bridge: Intel Corp.: Unknown device 27d2 (rev 01) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 00000000-00000fff Memory behind bridge: 00000000-000fffff Prefetchable memory behind bridge: 0000000000000000-0000000000000000 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [40] #10 [0141] Capabilities: [80] Message Signalled Interrupts: 64bit- Queue=0/0 Enable- Address: 00000000 Data: 0000 Capabilities: [90] #0d [0000] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable+ DSel=0 DScale=0 PME- 00:1d.0 USB Controller: Intel Corp.: Unknown device 27c8 (rev 01) (prog-if 00 [UHCI]) Subsystem: IBM: Unknown device 02f6 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 11 Region 4: I/O ports at 3000 [size=32] 00:1d.1 USB Controller: Intel Corp.: Unknown device 27c9 (rev 01) (prog-if 00 [UHCI]) Subsystem: IBM: Unknown device 02f6 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin B routed to IRQ 9 Region 4: I/O ports at 3020 [size=32] 00:1d.2 USB Controller: Intel Corp.: Unknown device 27ca (rev 01) (prog-if 00 [UHCI]) Subsystem: IBM: Unknown device 02f6 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin C routed to IRQ 11 Region 4: I/O ports at 3040 [size=32] 00:1d.3 USB Controller: Intel Corp.: Unknown device 27cb (rev 01) (prog-if 00 [UHCI]) Subsystem: IBM: Unknown device 02f6 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin D routed to IRQ 5 Region 4: I/O ports at 3060 [size=32] 00:1d.7 USB Controller: Intel Corp.: Unknown device 27cc (rev 01) (prog-if 20 [EHCI]) Subsystem: IBM: Unknown device 02f6 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 11 Region 0: Memory at d03c4000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] #0a [20a0] 00:1e.0 PCI bridge: Intel Corp. 82801BA/CA/DB PCI Bridge (rev e1) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=0a, subordinate=0a, sec-latency=32 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-0000000000000000 BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- Capabilities: [50] #0d [0000] 00:1f.0 ISA bridge: Intel Corp.: Unknown device 27b8 (rev 01) Subsystem: IBM: Unknown device 02f6 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [e0] #09 [100c] 00:1f.2 IDE interface: Intel Corp.: Unknown device 27c0 (rev 01) (prog-if 80 [Master]) Subsystem: IBM: Unknown device 02f6 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin B routed to IRQ 0 Region 0: I/O ports at <unassigned> Region 1: I/O ports at <unassigned> Region 2: I/O ports at <unassigned> Region 3: I/O ports at <unassigned> Region 4: I/O ports at 30b0 [size=16] Capabilities: [70] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:1f.3 SMBus: Intel Corp.: Unknown device 27da (rev 01) Subsystem: IBM: Unknown device 02f6 Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin B routed to IRQ 9 Region 4: I/O ports at 3080 [size=32] 02:00.0 Ethernet controller: Intel Corp.: Unknown device 108c (rev 03) Subsystem: IBM: Unknown device 02f6 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, cache line size 08 Interrupt: pin A routed to IRQ 16 Region 0: Memory at d0080000 (32-bit, non-prefetchable) [size=128K] Region 1: Memory at d0000000 (32-bit, non-prefetchable) [size=512K] Region 2: I/O ports at 4000 [size=32] Capabilities: [c8] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable+ DSel=0 DScale=1 PME- Capabilities: [d0] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [e0] #10 [0001] Best Regards. Xu

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[LinuxBIOS] Is there sched_clock equivalent in LB?
by Richard Smith April 27, 2006

April 27, 2006

On 4/26/06, Daniel Parthey <pada(a)chemonline.de> wrote: > Eric Poulsen schrieb: > > my MLB. The kernel printk uses sched_clock() to get the current time. > > Is there an equivalent call in LB? I've looked through the code base > > for files / code that has *clock* or *time* or something similar, but > > without much luck. > > I suppose MLB means VIA EPIA ML Board? > > On Intel compatible Pentium (or higher) boards like VIA EPIA, you could > read the Time Stamp Counter (TSC) CPU register which tells you the number cpu/x86/tsc/delay_tsc.c should have the info you need -- Richard A. Smith -- Richard A. Smith

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Re: [LinuxBIOS] Kernel crash output
by Peter Stuge April 26, 2006

April 26, 2006

You're sending replies only to me - let's keep it on the list for the benefit of others as well. Thanks! :) On Wed, Apr 26, 2006 at 11:20:59AM -0700, Eric Poulsen wrote: > 1) Use factory BIOS, re-save CMOS, Boot OS, Reboot later using LB > 2) Use factory BIOS, NOT re-save CMOS, Boot OS, Reboot later using LB > 3) Use factory BIOS, re-save CMOS, powerdown, boot use LB > 4) Use factory BIOS, NOT re-save CMOS, powerdown, boot use LB > 5) Other ? > > "re-save CMOS" means entering BIOS menu and choosing "save changes > and exit" > > When I have the crash problem, I have been using option #3. I'm > not sure if that answers your question =) Sorry, no. But the question was badly stated as well. :) More below. > >>I immediately flipped back to LB, and it worked as expected. > > > >Worked reliably or did not crash while you were looking? > > The crash _always_ occurs during initial kernel execution, before > 'init' starts. Depending on what the problem is, the system could crash later on as well, just that it hasn't been left running long enough or with such loads that the problem appears. > >Can you reliably reproduce the crash? If not there's no way to > >tell if the problem has been fixed or merely isn't manifesting > >itself at that particular point in time. > > > >Does just rebooting with LinuxBIOS produce different results than > >factory(resetCMOS)->LinuxBIOS? > > Rebooting with LB crashes every time, until I reset the CMOS with > the Factory BIOS. This is why I think it might be a CMOS issue -- > the crashing seems stateful. Ok! So the only successful way to boot LinuxBIOS under any circumstances is to first boot factory BIOS, have it do something (possibly rewrite CMOS, possibly something else) and then reboot into LinuxBIOS without powering off the system? If it works also when powering off between factory BIOS and LinuxBIOS, please leave the system powered off several hours up to a day and see it that works too. > >I second Richard on running memtest86, RAM problems can cause all > >sorts of funny things. > > I'll hit the ram test ASAP. I've had other weird issues, such as > the kernel taking a REALLY LONG time to initialize stuff. This is > new RAM, so hopefully still under warranty. Since this is code setting up the DRAM controller the RAM test also serves as a code test. > >Any system that requires special data to be in CMOS or anywhere else > >and does not validate this data before using it is broken. > > If by "system" you mean the BIOS, then I agree. Any system. Development 101 has to be "validate the input!" //Peter

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[LinuxBIOS] Adding a config option
by Richard Smith April 26, 2006

April 26, 2006

I'ts been awhile since I've messed with the config system and having some difficulity adding a new config option. I have modified the epia-m auto.c to have a ifdef wrapper around the section that disables the firewire bridge. I called it DISABLE_FIREWIRE. I added uses DISABLE_FIREWIRE to the Options.lb and setup a defaut. I then created a new target called epia-ml that just uses the epia-m mainboard but would disable the firewire disable section. But when I run buildtarget I still get: build_dir=via/epia-ml/epia-ml Configuring TARGET epia-ml Will place Makefile, crt0.S, etc. in via/epia-ml/epia-ml ===> ERROR: Can't use undefined option DISABLE_FIREWIRE via/epia-ml/Config.lb:0 src/mainboard/via/epia-m/Options.lb:0 Where else do I have to add my new config option so the buld system knwos about it? -- Richard A. Smith

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Re: [LinuxBIOS] Overview
by Peter Stuge April 26, 2006

April 26, 2006

On Wed, Apr 26, 2006 at 10:40:28AM -0700, Eric Poulsen wrote: > Cool, I'll check out the DOM stuff -- I was wondering how I was > going to mount my CF/IDE unit inside my tiny case. The CF/IDE > adapter does have the advantage that I could simply pull it out, > put a new kernel on it (using another cpu) and plug it back in. > I wonder if you can hot-swap CF/IDE, provided you unmount it? That depends on the adapter. I just added a few adapters, one with hotswap support, to: http://wiki.linuxbios.org/index.php/FAQ#What_kind_of_hardware_tools_do_I_ne… //Peter

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[LinuxBIOS] Overview
by m＠de-minimis.co.uk April 26, 2006

April 26, 2006

Dear All, I'm completely new to LinuxBios, and I'm trying to understand exactly what it does, and what it offers. Trying to decide exactly how interested I am. Could you please forgive my ignorance and clarify the following for me please: Does LinuxBios run on the main processor or on some auxiliary processor? What is the typical power consumption of a LinuxBios moboard running the minimum number of devices to do basic communication over ethernet - hopefully only the moboard and the network card if it isn't already on the moboard will require power, then I need to know processor consumption - here the earlier question about what does the processing becomes relevant. Can LinuxBios be used to do complicated wake-on lan? Here minimal power consumption in the idle state becomes important to me. (question of fairly high interest to me) Does LinuxBios help with running multiple operating systems simultaneously? (high interest) Does it accelerate booting, because where previously first the bios loaded, then grub, then the OS proper, now perhaps booting can go straight from LinuxBios to OS? How often can one typically write to the bios before it won't take any more changes? I understand it's flash, so I expect few thousand times, more if one rotates which memory blocks one uses, but on the other hand this isn't exactly flash that is designed to be rewritten very often, as far as I understand anyway! Can one fairly easily and at a competitive price buy replacement chips? I very much appreciate any help you can give, because you've already done this kind of stuff. A short introduction is probably in order: I'm a mathematician, so a bit of an amateur where computer science is concerned. I'm getting into writing linux device drivers at the moment. Best Wishes, Max

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Re: [LinuxBIOS] What's stored in the CMOS by LB?
by Goodrich,Steven April 25, 2006

April 25, 2006

Exception 6 is Invalid Opcode. This usually means that ES:EIP is pointing to data or to garbage (stack error?). It could mean that you're not at the right privilege level for the specific instruction at CS:EIP. -- Steve G. -----Original Message----- From: linuxbios-bounces(a)linuxbios.org [mailto:linuxbios-bounces@linuxbios.org] On Behalf Of Ronald G Minnich Sent: Tuesday, April 25, 2006 12:44 PM To: Eric Poulsen Cc: LinuxBIOS Subject: Re: [LinuxBIOS] What's stored in the CMOS by LB? Eric Poulsen wrote: > > 1) Does LB store anything in the CMOS? it can. It does store a few abouts about the type of boot that occurred (fallback or normal). > 2) If yes, is there anything in there that could become corrupted and > cause "weird issues" as described above? What's exception 6? I don't recall. sometimes clocking info is stored in CMOS. There could be a collision here. If you can tell more it would be good to know. ron -- linuxbios mailing list linuxbios(a)linuxbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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[LinuxBIOS] Q's regarding pci_routing_fixup() in src/southbridge/via/vt8235/vt8235_lpc.c
by Eric Poulsen April 25, 2006

April 25, 2006

If the southbridge init code assigns irqs to nonexistent devices. 1) Is this slow? 2) Does it matter if it assigns an irq to a nonexistent device? static void pci_routing_fixup(struct device *dev) { printk_info("%s: dev is %p\n", __FUNCTION__, dev); /* set up PCI IRQ routing */ pci_write_config8(dev, 0x55, pciIrqs[0] << 4); pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) ); pci_write_config8(dev, 0x57, pciIrqs[3] << 4); // firewire built into southbridge printk_info("setting firewire\n"); pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins)); [... usb, sound, ethernet, vga, pci slots ...] // Cardbus slot printk_info("setting cardbus slot\n"); pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins)); printk_spew("%s: DONE\n", __FUNCTION__); }

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[LinuxBIOS] gx2 status
by Ronald G Minnich April 25, 2006

April 25, 2006

as of today, we have got ethernet and external uart up on rumba, so we now have a networked node. OLPC patches are next, then graphics, then ... I'm also planning to put Plan 9 in FLASH on the lippert frontrunner, but that's next week ... ron

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