coreboot October 2004

coreboot@coreboot.org

45 participants
197 discussions

Epia-N
by Bari Ari 27 Oct '04

27 Oct '04

Has anyone started working on a port to the Epia-N yet? It uses the new CN400 northbridge and the VT8237 sothbridge. -Bari

4 4

RE: S2885 -- spare 4s in rebooting
by YhLu 27 Oct '04

27 Oct '04

Under normal mode, using jmp __cpu_reset, the stage is rather faster. Copying LinuxBIOS to ram. <------- here take sometime ---skipped by Soft2_reset Jumping to LinuxBIOS. <------------------ skipped by Soft2_reset LinuxBIOS-1.1.72.0_Fallback Tue Oct 26 18:48:45 PDT 2004 rebooting...-----> -----Original Message----- From: YhLu Sent: Wednesday, October 27, 2004 11:00 AM To: ebiederman(a)lnxi.com Cc: Ronald G. Minnich; linuxbios(a)clustermatic.org Subject: RE: S2885 -- spare 4s in rebooting With cpu_reset ~ # reboot INIT: Sending processes the TERM signal INIT: Cmos information update Getting settings Stop port mapper Shutdown syslog daemon Shutdown klogd daemon Sending all processes the TERM signal... Sending all processes the KILL signal.. Please, stand by while rebooting the system ... Restarting system. Copying LinuxBIOS to ram. <------- here take sometime ---skipped by Soft2_reset Jumping to LinuxBIOS. <------------------ skipped by Soft2_reset LinuxBIOS-1.1.72.0_Fallback Tue Oct 26 18:48:45 PDT 2004 rebooting...-----> skipped by soft2_reset LinuxBIOS-1.1.72.0_Fallback Tue Oct 26 18:48:45 PDT 2004 starting... Ram1.00 Ram1.01 Ram2.00 Ram2.01 Ram3 Initializing memory: done Initializing memory: done Clearing initial memory region: done Ram4 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.72.0_Fallback Tue Oct 26 18:48:45 PDT 2004 booting... Finding PCI configuration type. PCI: Using configuration type 1 -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Wednesday, October 27, 2004 10:16 AM To: YhLu Cc: Ronald G. Minnich; linuxbios(a)clustermatic.org Subject: Re: S2885 -- spare 4s in rebooting YhLu <YhLu(a)tyan.com> writes: > Spare 4s for rebooting > > I add some comments in s2885/auto.c. > > In auto.c call soft2_reset directly instead of jmp to __cpu_reset Hmm. That does seem to have some merit. Where are you seeing the code run slowly? In particular I am wondering if this is an mtrr setup problem or something else you are avoiding. Eric _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

1 0

[COMMI] Merge recover status...
by ebiederman＠lnxi.com 27 Oct '04

27 Oct '04

I should have fixed the sizeram function for all of the x86 ports. So while I don't expect everything to work it should mostly a matter of cleanup of the configuration files now, so it should be pretty easy. The one remaining x86 gotcha is likely adding support for the via c3 and the transmeta TM5800 cpus that it looks like we try and support. It looks like we have a lot of ports that were started and not completed :( PPC is still broken. I need to be fresh to tackle fixing it up. At the moment I don't have the slightest clue what the PPC code flow looks like. I don't see hide nor hare of the dynamic device tree in the ppc code I have looked at, so I don't know yet where to start to convert the code. Anyway the maelstrom of changes is settling down. So feel free to take your favorite port and see if you can get it building or running again. A build success report from the Stefan's all port builder would will be interesting. Eric sizeram removal/conversion. - mem.h and sizeram.h and all includes killed because the are no longer needed. - linuxbios_table.c updated to directly look at the device tree for occupied memory areas. - first very incomplete stab a converting the ppc code to work with the dynamic device tree - Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources). - First stab at Pentium-M support - add part/init_timer.h making init_timer conditional until there is a better way of handling it. - Converted all of the x86 sizeram to northbridge set_resources functions. CVS: ---------------------------------------------------------------------- CVS: Enter Log. Lines beginning with `CVS:' are removed automatically CVS: CVS: Committing in . CVS: CVS: Modified Files: CVS: src/arch/i386/boot/linuxbios_table.c CVS: src/arch/i386/boot/linuxbios_table.h CVS: src/arch/ppc/boot/linuxbios_table.c src/arch/ppc/boot/tables.c CVS: src/arch/ppc/lib/cpu.c src/arch/ppc/lib/cpuid.c CVS: src/boot/hardwaremain.c src/config/Options.lb CVS: src/cpu/amd/model_fxx/Config.lb src/cpu/x86/tsc/Config.lb CVS: src/devices/device.c src/include/part/fallback_boot.h CVS: src/mainboard/arima/hdama/Options.lb CVS: src/mainboard/arima/hdama/auto.c CVS: src/mainboard/digitallogic/adl855pc/Config.lb CVS: src/mainboard/emulation/qemu-i386/Config.lb CVS: src/northbridge/amd/amdk8/northbridge.c CVS: src/northbridge/emulation/qemu-i386/northbridge.c CVS: src/northbridge/intel/e7501/northbridge.c CVS: src/northbridge/intel/i855pm/northbridge.c CVS: src/northbridge/motorola/mpc107/mpc107.c CVS: src/northbridge/transmeta/tm5800/northbridge.c CVS: src/northbridge/via/vt8601/northbridge.c CVS: src/northbridge/via/vt8623/northbridge.c CVS: src/southbridge/intel/i82870/p64h2_pci_parity.c CVS: Added Files: CVS: src/include/part/init_timer.h CVS: Removed Files: CVS: src/include/mem.h src/include/part/sizeram.h CVS: ----------------------------------------------------------------------

2 4

RE: [COMMI] Merge recover status...
by YhLu 27 Oct '04

27 Oct '04

Amd k8 northbridge.c line 717 for(i = 0; i < 7; i++) { is it shoule be 8 instead of 7? Regards YH -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Wednesday, October 27, 2004 10:10 AM To: Ronald G. Minnich Cc: LinuxBIOS Subject: Re: [COMMI] Merge recover status... "Ronald G. Minnich" <rminnich(a)lanl.gov> writes: > On Wed, 27 Oct 2004, Eric W. Biederman wrote: > > > The one remaining x86 gotcha is likely adding support for the > > via c3 and the transmeta TM5800 cpus that it looks like we try > > and support. It looks like we have a lot of ports that were > > started and not completed :( > > yes, transmeta refused to help with the details of DDR on the new cpu, in > spite of promises to do so, hence that effort (with a 3rd party) ended. > > A shame. Yes. Somehow I would have suspected the procedure would have been the same, or simpler though. Dump the SPD values from the DIMMs into the northbridge. Eric _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

2 1

RE: S2885 -- spare 4s in rebooting
by YhLu 27 Oct '04

27 Oct '04

With cpu_reset ~ # reboot INIT: Sending processes the TERM signal INIT: Cmos information update Getting settings Stop port mapper Shutdown syslog daemon Shutdown klogd daemon Sending all processes the TERM signal... Sending all processes the KILL signal.. Please, stand by while rebooting the system ... Restarting system. Copying LinuxBIOS to ram. <------- here take sometime ---skipped by Soft2_reset Jumping to LinuxBIOS. <------------------ skipped by Soft2_reset LinuxBIOS-1.1.72.0_Fallback Tue Oct 26 18:48:45 PDT 2004 rebooting...-----> skipped by soft2_reset LinuxBIOS-1.1.72.0_Fallback Tue Oct 26 18:48:45 PDT 2004 starting... Ram1.00 Ram1.01 Ram2.00 Ram2.01 Ram3 Initializing memory: done Initializing memory: done Clearing initial memory region: done Ram4 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.72.0_Fallback Tue Oct 26 18:48:45 PDT 2004 booting... Finding PCI configuration type. PCI: Using configuration type 1 -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Wednesday, October 27, 2004 10:16 AM To: YhLu Cc: Ronald G. Minnich; linuxbios(a)clustermatic.org Subject: Re: S2885 -- spare 4s in rebooting YhLu <YhLu(a)tyan.com> writes: > Spare 4s for rebooting > > I add some comments in s2885/auto.c. > > In auto.c call soft2_reset directly instead of jmp to __cpu_reset Hmm. That does seem to have some merit. Where are you seeing the code run slowly? In particular I am wondering if this is an mtrr setup problem or something else you are avoiding. Eric

1 0

RE: S2885 -- spare 4s in rebooting
by YhLu 27 Oct '04

27 Oct '04

Spare 4s for rebooting I add some comments in s2885/auto.c. In auto.c call soft2_reset directly instead of jmp to __cpu_reset #if 0 asm volatile ("jmp __cpu_reset"); #else /* cpu reset also reset the memtroller ???? need soft_reset to reset all except keep HT link freq and width */ /* So we don't need to 1. jmp to __cpu_reset 2. jmp to __main to copy ROM to ram (It costs some time) 3. call hardwaremain(), it will according to boot_complete to issue hard_reset in southbridge. (Actually it is soft2_reset(); --- without call hard_reset, the memory is corrupted. We will call soft2_reset directly to spare time in 1 and 2 and 3.2 */ distinguish_cpu_resets(); soft2_reset(); #endif

2 1

Q: Which is used the 855pm or the i855pm code?
by ebiederman＠lnxi.com 27 Oct '04

27 Oct '04

I am walking through the code converting the sizeram() functions and have run across a duplicate 855pm and the i855pm. The digitallogic/adl855pc is using the i855pm, so that appears to be the active one. Is there a reason we have two of these? If not can we just delete src/northbridge/intel/855pm? Eric

2 2

RE: S2885
by YhLu 27 Oct '04

27 Oct '04

I will try !curdev->have_resources Regards YH -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Tuesday, October 26, 2004 9:28 PM To: YhLu Cc: Ronald G. Minnich; linuxbios(a)clustermatic.org Subject: Re: S2885 YhLu <YhLu(a)tyan.com> writes: > Eric, > > So even the pnp is disabled, the fixed value should be there. > > I wonder if add if(!curdev->enabled) continue; > In find_largest_resource is good way to fix it. It is a little weird but that sounds like a sane way to do it. Although I think a test of !curdev->have_resources is a little better. What puzzles me is that even disabled you seem to have had all of the resources specified so they should have had IORESOURCE_FIXED set. So I don't see how they were being looked at. Eric

1 0

RE: S2885
by YhLu 27 Oct '04

27 Oct '04

Eric, So even the pnp is disabled, the fixed value should be there. I wonder if add if(!curdev->enabled) continue; In find_largest_resource is good way to fix it. Regards YH static void find_largest_resource(struct pick_largest_state *state, struct bus *bus, unsigned long type_mask, unsigned long type) { struct device *curdev; for(curdev = bus->children; curdev; curdev = curdev->sibling) { int i; if(!curdev->enabled) continue; chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end device pnp 2e.6 off # CIR io 0x60 = 0x90 end device pnp 2e.7 off # GAME_MIDI_GIPO1 io 0x60 = 0x70 io 0x62 = 0x74 irq 0x70 = 5 end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end end _____ From: YhLu Sent: Tuesday, October 26, 2004 3:29 PM To: ebiederman(a)lnxi.com Cc: Ronald G. Minnich; linuxbios(a)clustermatic.org Subject: RE: S2885 I add print_debug in device.c if (resource->flags & IORESOURCE_FIXED) { printk_debug("\t\t%s, base=%08Lx, limit=%08Lx\r\n", dev_path(dev), resource->base, resource->limit); continue; } Found some interesting result PNP: 002e.0, base=000003f0, limit=000007ff PNP: 002e.1, base=00000378, limit=000007ff PNP: 002e.2, base=000003f8, limit=000007ff PNP: 002e.3, base=000002f8, limit=000007ff PNP: 002e.b, base=00000290, limit=00000fff PNP: 002e.5, base=00000060, limit=ffffffff PNP: 002e.5, base=00000064, limit=ffffffff 1. It real does the continue. 2. it process disabled device,if it is get the fixed values in Config.lb PNP: 002e.0 enabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled In Config.lb chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GAME_MIDI_GIPO1 device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end end in superio.c static struct pnp_info pnp_dev_info[] = { { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, // No 4 { 0,}, { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4}, }, { &ops, W83627HF_GPIO2,}, { &ops, W83627HF_GPIO3,}, { &ops, W83627HF_ACPI, PNP_IRQ0, }, { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, };

3 2

RE: S2885
by YhLu 26 Oct '04

26 Oct '04

I add print_debug in device.c if (resource->flags & IORESOURCE_FIXED) { printk_debug("\t\t%s, base=%08Lx, limit=%08Lx\r\n", dev_path(dev), resource->base, resource->limit); continue; } Found some interesting result PNP: 002e.0, base=000003f0, limit=000007ff PNP: 002e.1, base=00000378, limit=000007ff PNP: 002e.2, base=000003f8, limit=000007ff PNP: 002e.3, base=000002f8, limit=000007ff PNP: 002e.b, base=00000290, limit=00000fff PNP: 002e.5, base=00000060, limit=ffffffff PNP: 002e.5, base=00000064, limit=ffffffff 1. It real does the continue. 2. it process disabled device,if it is get the fixed values in Config.lb PNP: 002e.0 enabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled In Config.lb chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GAME_MIDI_GIPO1 device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end end in superio.c static struct pnp_info pnp_dev_info[] = { { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, // No 4 { 0,}, { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4}, }, { &ops, W83627HF_GPIO2,}, { &ops, W83627HF_GPIO3,}, { &ops, W83627HF_ACPI, PNP_IRQ0, }, { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, };

1 0

← Newer
1
2
3
4
5
6
7
...
20
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot October 2004