Change in coreboot[master]: soc/intel/cannonlake: Use common bootblock basecode

[Angel Pons (Code Review)]

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50956 )

Change subject: soc/intel/cannonlake: Use common bootblock basecode
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Patch Set 2:

(1 comment)

File src/soc/intel/cannonlake/bootblock/bootblock.c:

https://review.coreboot.org/c/coreboot/+/50956/comment/12bfdfe3_4674a81e 
PS2, Line 64: 	/*
            : 	 * Clear the GPI interrupt status and enable registers. These
            : 	 * registers do not get reset to default state when booting from S5.
            : 	 */
            : 	gpi_clear_int_cfg();
> How about bootblock_pch_init() for now, and I'll try to follow up later to move it to common code .

CB:51148