Michael Büchler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock/h77pro4-m: add new mainboard ......................................................................
mb/asrock/h77pro4-m: add new mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM.
The port was initially done with autoport. It is quite similar to the ASRock B75 Pro4-M which is already supported by coreboot.
Working: - Console output on the serial port of the Super I/O - Native RAM initialization with two DIMMs - Core i5-2500 CPU
Not working: - Currently fails during PCIe bus scans
Untested: - Ivy Bridge - All four DIMM slots - The rest
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler michael.buechler@posteo.net --- A src/mainboard/asrock/h77pro4-m/Kconfig A src/mainboard/asrock/h77pro4-m/Kconfig.name A src/mainboard/asrock/h77pro4-m/Makefile.inc A src/mainboard/asrock/h77pro4-m/acpi/ec.asl A src/mainboard/asrock/h77pro4-m/acpi/platform.asl A src/mainboard/asrock/h77pro4-m/acpi/superio.asl A src/mainboard/asrock/h77pro4-m/acpi_tables.c A src/mainboard/asrock/h77pro4-m/board_info.txt A src/mainboard/asrock/h77pro4-m/devicetree.cb A src/mainboard/asrock/h77pro4-m/dsdt.asl A src/mainboard/asrock/h77pro4-m/early_init.c A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads A src/mainboard/asrock/h77pro4-m/gpio.c A src/mainboard/asrock/h77pro4-m/hda_verb.c A src/mainboard/asrock/h77pro4-m/mainboard.c 15 files changed, 612 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45317/1
diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig b/src/mainboard/asrock/h77pro4-m/Kconfig new file mode 100644 index 0000000..daa1526 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/Kconfig @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_H77PRO4_M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_NUVOTON_NCT6776 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + select DRIVERS_ASMEDIA_ASPM_BLACKLIST # FIXME copied from B75 Pro3M + +config MAINBOARD_DIR + string + default asrock/h77pro4-m + +config MAINBOARD_PART_NUMBER + string + default "H77 Pro4-M" + +config VGA_BIOS_FILE + string + default "pci8086,0152.rom" + +config VGA_BIOS_ID + string + default "8086,0152" + +#config DRAM_RESET_GATE_GPIO # FIXME: check this +# int +# default 60 +# +#config USBDEBUG_HCD_INDEX # FIXME: check this +# int +# default 2 +endif diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig.name b/src/mainboard/asrock/h77pro4-m/Kconfig.name new file mode 100644 index 0000000..03873b9 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_H77PRO4_M + bool "H77 Pro4-M" diff --git a/src/mainboard/asrock/h77pro4-m/Makefile.inc b/src/mainboard/asrock/h77pro4-m/Makefile.inc new file mode 100644 index 0000000..a0d1155 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/h77pro4-m/acpi/ec.asl b/src/mainboard/asrock/h77pro4-m/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asrock/h77pro4-m/acpi/platform.asl b/src/mainboard/asrock/h77pro4-m/acpi/platform.asl new file mode 100644 index 0000000..146be65 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/h77pro4-m/acpi/superio.asl b/src/mainboard/asrock/h77pro4-m/acpi/superio.asl new file mode 100644 index 0000000..1eae4b2 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi/superio.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e + +#define NCT6776_SHOW_SP1 1 +#define NCT6776_SHOW_KBC 1 + +#include "superio/nuvoton/nct6776/acpi/superio.asl" diff --git a/src/mainboard/asrock/h77pro4-m/acpi_tables.c b/src/mainboard/asrock/h77pro4-m/acpi_tables.c new file mode 100644 index 0000000..f8364ab --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi_tables.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asrock/h77pro4-m/board_info.txt b/src/mainboard/asrock/h77pro4-m/board_info.txt new file mode 100644 index 0000000..5f86088d --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/H77%20Pro4-M/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb new file mode 100644 index 0000000..8c5d0e5 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + #register "gfx.use_spread_spectrum_clock" = "0" # from B75 Pro3-M + #register "gfx" = "GMA_STATIC_DISPLAYS(0)" # from autoport + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1849 0x0100 + end + device pci 01.0 off # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0102 + end + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "0" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1849 0x1e31 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0x1e3a + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x1e2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x8892 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1849 0x1e10 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 on # PCIe Port #6 - RTL8111E GbE + subsystemid 0x1849 0x1e1a + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 on # PCIe Port #8 - ASM1061 SATA Controller + subsystemid 0x1849 0x1e1e + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x1e26 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1e4a + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # TODO verify + # global + irq 0x1c = 0x80 + irq 0x27 = 0xc0 + irq 0x2a = 0x62 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-9 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA + device pnp 2e.9 off end # GPIO2-5 + device pnp 2e.a on # ACPI + # TODO verify + irq 0xe0 = 0x01 + irq 0xe3 = 0x14 + irq 0xe6 = 0x4c + #irq 0xe9 = 0x02 + irq 0xf0 = 0x20 + end + device pnp 2e.b off end # HWM, front panel LED + device pnp 2e.d on end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f on end # GPIO Push-Pull or Open-drain + device pnp 2e.14 on end # SVID + device pnp 2e.16 on end # Deep Sleep + device pnp 2e.17 on end # GPIOA + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1849 0x1e02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x1e22 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/asrock/h77pro4-m/dsdt.asl b/src/mainboard/asrock/h77pro4-m/dsdt.asl new file mode 100644 index 0000000..38f5325 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c new file mode 100644 index 0000000..ca79de8 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/early_init.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <superio/nuvoton/common/nuvoton.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + /* Set GPIOs on superio, enable UART */ + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + pnp_set_logical_device(SERIAL_DEV); + + pnp_write_config(SERIAL_DEV, 0x1b, 0x68); // bit 4 now cleared -> pin 95 GP24 + pnp_write_config(SERIAL_DEV, 0x1c, 0x80); // Pin 54 AFD#, pin 55 STB# + // default 0x64, vendor BIOS 0x5c + // bit 3 '1' -> CPUFANOUT push-pull instead of open drain + // bit 4 '1' -> SYSFANOUT push-pull instead of open drain + // bit 5 '0' -> AUXFANOUT open drain instead of push-pull + pnp_write_config(SERIAL_DEV, 0x24, 0x5c); // Pin 88-93 GP75-GP70, Pin 86-87 GP77-76 + pnp_write_config(SERIAL_DEV, 0x27, 0xc0); // Pin 88-93 GP75-GP70, Pin 86-87 GP77-76 + // default 0xc0 (bits 7,6 set), vendor BIOS 0x62 (bit 7 cleared, bit 1 set) + // bit 7 is '0' --> pins 29-36 COM A instead of GPIO8 (GP8*) + // bit 6 is '1' --> pins 116-123 are VIDI[7-0] + // bit 1 is '1' --> pin 56,57 are GP23,22 instead of MCLK,MDAT + // bit 0 is '0' --> pins 58,59 stay as KCLK,KDAT + pnp_write_config(SERIAL_DEV, 0x2a, 0x62); // Pin 29-36 COM A + pnp_write_config(SERIAL_DEV, 0x2b, 0x08); // Pin 81 GP32 instead of CPUPWRGD + pnp_write_config(SERIAL_DEV, 0x2c, 0x80); // Pin 113,115 GPA0,PECI instead of TSIC,TSID + + // FIXME 0x13,0x14 "Device IRQ Polarity Selection" are set by the vendor BIOS + + /* random note + * 24M_48M_SEL strap can be read on config reg 0x2f bit 0, it's '1' -> 48 MHz + * also LPT_EN is '1' on bit 1 of 0x2f -> LPT enabled + */ + + nuvoton_pnp_exit_conf_state(SERIAL_DEV); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + // generated by autoport + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1405); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads b/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads new file mode 100644 index 0000000..133fde5 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/h77pro4-m/gpio.c b/src/mainboard/asrock/h77pro4-m/gpio.c new file mode 100644 index 0000000..84f4564 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/gpio.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/h77pro4-m/hda_verb.c b/src/mainboard/asrock/h77pro4-m/hda_verb.c new file mode 100644 index 0000000..9998266 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x18498892, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18498892), + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19950), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214120), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/h77pro4-m/mainboard.c b/src/mainboard/asrock/h77pro4-m/mainboard.c new file mode 100644 index 0000000..4322c1e --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +};
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock/h77pro4-m: add new mainboard ......................................................................
Patch Set 1:
(27 comments)
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 3: H77PRO4_M I'd use `H77_PRO4_M`
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 12: # FIXME: check this This is correct
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 17: select DRIVERS_ASMEDIA_ASPM_BLACKLIST # FIXME copied from B75 Pro3M Sort this alphabetically?
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 27: config VGA_BIOS_FILE : string : default "pci8086,0152.rom" : : config VGA_BIOS_ID : string : default "8086,0152" Depends on the installed CPU. I'd drop it.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 35: #config DRAM_RESET_GATE_GPIO # FIXME: check this If suspend/resume works, drop this
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 39: #config USBDEBUG_HCD_INDEX # FIXME: check this If you can test usbdebug, then adjust it. Otherwise, drop it.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 4: bootblock-y += gpio.c I think GPIO isn't needed in bootblock.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 11: #include "superio/nuvoton/nct6776/acpi/superio.asl" This ACPI code is rather broken, and at least Windows 10 will complain about it. I think the best approach is to switch to a dynamically-generated SSDT, but it's not done yet.
If you want to try Windows on this board, check Asus P8Z77-V LX2 or Asrock B85M Pro4 (I ported both boards and both boot to Windows 10 with TianoCore)
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 9: /* The lid is open by default. */ : gnvs->lids = 1; No lid on a desktop
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 4: #register "gfx.use_spread_spectrum_clock" = "0" # from B75 Pro3-M : #register "gfx" = "GMA_STATIC_DISPLAYS(0)" # from autoport Drop both
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 6: register "gpu_cpu_backlight" = "0x00000000" : register "gpu_dp_b_hotplug" = "4" : register "gpu_dp_c_hotplug" = "4" : register "gpu_dp_d_hotplug" = "4" : register "gpu_panel_port_select" = "0" : register "gpu_panel_power_backlight_off_delay" = "0" : register "gpu_panel_power_backlight_on_delay" = "0" : register "gpu_panel_power_cycle_delay" = "4" : register "gpu_panel_power_down_delay" = "0" : register "gpu_panel_power_up_delay" = "0" : register "gpu_pch_backlight" = "0x00000000" None of these apply
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 26: end Please "pick up" the `end` for empty blocks (put them on the previous line)
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 32: Host bridge Host bridge Once is enough.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 35: off on
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 42: register "docking_supported" = "0" The devicetree becomes a struct, so all fields that are set to zero can be dropped
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 46: register "gen4_dec" = "0x00000000" : register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" : register "pcie_port_coalesce" = "0" The devicetree becomes a struct, so all fields that are set to zero can be dropped
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 105: # TODO verify superiotool is your friend 😊
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 106: # global : irq 0x1c = 0x80 : irq 0x27 = 0xc0 : irq 0x2a = 0x62 I prefer to set these in `mainboard_config_superio` (early_init.c)
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 147: SATA Controller 1 SATA (AHCI)
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 153: SATA Controller 2 SATA (Legacy)
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 3: One blank line is enough.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 24: #include <drivers/intel/gma/acpi/default_brightness_levels.asl> Nope, no brightness for you. This used to be necessary, but it isn't anymore.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 37: SERIAL_DEV I'd do what mb/asus/p8z77-v_lx2 does, which should be clearer. The registers you're writing to aren't specific to any LDN, so `GLOBAL_DEV` is more reasonable
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 67: pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); Probably not required.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 70: /* FIXME: Put proper SPD map here. */ This is probably correct. One simple way to check is to try booting with only one DIMM. Repeat for all four slots. If all slots boot correctly, then it's correct.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 20: LVDS, : eDP I don't think so. Replace with:
others => Disabled
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 10: GMA_INT15_ACTIVE_LFP_INT_LVDS That's wrong. If you don't want to use a VBIOS, drop the entire file and `select INTEL_INT15` from Kconfig.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock/h77pro4-m: add new mainboard ......................................................................
Patch Set 1: Code-Review+1
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock/h77pro4-m: add new mainboard ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 21: default asrock/h77pro4-m default "asrock/h77pro4-m"
(please use "" for strings)
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 5: #include <device/pci_def.h> maybe not needed
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45317
to look at the new patch set (#2).
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
mb/asrock: Add ASRock H77 Pro4-M mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM.
The port was initially done with autoport. It is quite similar to the ASRock B75 Pro4-M which is already supported by coreboot.
Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 mouse or keyboard - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - Rear USB3 ports with reasonable transfer rates - All eight SATA ports - Console output on the serial port of the Super I/O - SeaBIOS 1.14.0 to boot slackware64 - SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS) - External flashing with flashrom-1.2 and a Raspberry Pi 1
WAS working until I changed some things inbetween: - S3 suspend/resume from either Linux or Windows 10. Now it immediately resumes.
Not working: - Booting from the two SATA ports provided by the ASM1061 - Fan control with the NCT6776D Super I/O - Internal flashing with flashrom-1.2 (no write permission on BIOS region). - The ME on my board. While measuring on the Super I/O pins during S3 suspend I probably shorted something. Since then the ME has trouble coming up and the vendor BIOS doesn't work anymore. coreboot works. I'm now testing with `me_cleaner -S` applied.
Untested: - VBT (it is included, though) - Internal USB3 header (2 ports) - SATA 6Gb/s - Rear eSATA connector - Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler michael.buechler@posteo.net --- A src/mainboard/asrock/h77pro4-m/Kconfig A src/mainboard/asrock/h77pro4-m/Kconfig.name A src/mainboard/asrock/h77pro4-m/Makefile.inc A src/mainboard/asrock/h77pro4-m/acpi/ec.asl A src/mainboard/asrock/h77pro4-m/acpi/platform.asl A src/mainboard/asrock/h77pro4-m/acpi/superio.asl A src/mainboard/asrock/h77pro4-m/acpi_tables.c A src/mainboard/asrock/h77pro4-m/board_info.txt A src/mainboard/asrock/h77pro4-m/data.vbt A src/mainboard/asrock/h77pro4-m/devicetree.cb A src/mainboard/asrock/h77pro4-m/dsdt.asl A src/mainboard/asrock/h77pro4-m/early_init.c A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads A src/mainboard/asrock/h77pro4-m/gpio.c A src/mainboard/asrock/h77pro4-m/hda_verb.c 15 files changed, 554 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45317/2
Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 2:
(29 comments)
Your feedback was a great help for getting things in a proper way. Then I messed up my Super I/O or PCH when measuring at some Super I/O pins and things got weird. Next step might be soldering a new NCT6776D once it arrives.. and: fixing S3; making this a variant of mb/asrock/b75pro3-m
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 3: H77PRO4_M
I'd use `H77_PRO4_M`
Yes. On the other hand the B75 Pro3-M uses B75PRO3_M and as per your suggestion I'm considering to make this board a variant of it. Then I think it should be consistent.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 12: # FIXME: check this
This is correct
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 17: select DRIVERS_ASMEDIA_ASPM_BLACKLIST # FIXME copied from B75 Pro3M
Sort this alphabetically?
Done (if I still know the ABC correctly)
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 21: default asrock/h77pro4-m
default "asrock/h77pro4-m" […]
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 27: config VGA_BIOS_FILE : string : default "pci8086,0152.rom" : : config VGA_BIOS_ID : string : default "8086,0152"
Depends on the installed CPU. I'd drop it.
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 35: #config DRAM_RESET_GATE_GPIO # FIXME: check this
If suspend/resume works, drop this
It does! \o/
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 39: #config USBDEBUG_HCD_INDEX # FIXME: check this
If you can test usbdebug, then adjust it. Otherwise, drop it.
Done. Can't test it.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 4: bootblock-y += gpio.c
I think GPIO isn't needed in bootblock.
Build fails when I remove it. It seems to be called in src/southbridge/intel/bd82x6x/early_pch.c:early_pch_init(). Hence I'm leaving it in there.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 11: #include "superio/nuvoton/nct6776/acpi/superio.asl"
This ACPI code is rather broken, and at least Windows 10 will complain about it. […]
I was able to install and use Windows 10 without a change here, but later I will try what you suggested.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 9: /* The lid is open by default. */ : gnvs->lids = 1;
No lid on a desktop
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 4: #register "gfx.use_spread_spectrum_clock" = "0" # from B75 Pro3-M : #register "gfx" = "GMA_STATIC_DISPLAYS(0)" # from autoport
Drop both
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 6: register "gpu_cpu_backlight" = "0x00000000" : register "gpu_dp_b_hotplug" = "4" : register "gpu_dp_c_hotplug" = "4" : register "gpu_dp_d_hotplug" = "4" : register "gpu_panel_port_select" = "0" : register "gpu_panel_power_backlight_off_delay" = "0" : register "gpu_panel_power_backlight_on_delay" = "0" : register "gpu_panel_power_cycle_delay" = "4" : register "gpu_panel_power_down_delay" = "0" : register "gpu_panel_power_up_delay" = "0" : register "gpu_pch_backlight" = "0x00000000"
None of these apply
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 26: end
Please "pick up" the `end` for empty blocks (put them on the previous line)
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 32: Host bridge Host bridge
Once is enough.
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 35: off
on
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 42: register "docking_supported" = "0"
The devicetree becomes a struct, so all fields that are set to zero can be dropped
Done. Thanks for explaining why.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 46: register "gen4_dec" = "0x00000000" : register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" : register "pcie_port_coalesce" = "0"
The devicetree becomes a struct, so all fields that are set to zero can be dropped
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 105: # TODO verify
superiotool is your friend 😊
Indeed!
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 106: # global : irq 0x1c = 0x80 : irq 0x27 = 0xc0 : irq 0x2a = 0x62
I prefer to set these in `mainboard_config_superio` (early_init. […]
Put into early_init.c:bootblock_mainboard_early_init(). Was already in there actually.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 147: SATA Controller 1
SATA (AHCI)
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 153: SATA Controller 2
SATA (Legacy)
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 3:
One blank line is enough.
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 24: #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
Nope, no brightness for you. This used to be necessary, but it isn't anymore.
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 5: #include <device/pci_def.h>
maybe not needed
Indeed, thanks. Done.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 37: SERIAL_DEV
I'd do what mb/asus/p8z77-v_lx2 does, which should be clearer. […]
Done
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 67: pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
Probably not required.
Nope, doesn't seem to be.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 70: /* FIXME: Put proper SPD map here. */
This is probably correct. One simple way to check is to try booting with only one DIMM. […]
Thanks for explaining how to check. Boots with a single DIMM in any slot.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 20: LVDS, : eDP
I don't think so. Replace with: […]
Done. I looked at `xrandr` output and saw which are needed.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 10: GMA_INT15_ACTIVE_LFP_INT_LVDS
That's wrong. […]
Uhm I think it was never actually compiled or linked. Dropped the file. VBIOS works with and without it.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 2: Code-Review+1
(15 comments)
Looks good, I hope you can recover the board. I once replaced the EC on a laptop mainboard and it made no difference at all... Then I found a shorted MOSFET and the board came back to life. 😊
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@14 PS2, Line 14: Pro4 Pro3
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@19 PS2, Line 19: - PS/2 mouse or keyboard Both work, only one port?
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@25 PS2, Line 25: - All eight SATA ports 6 on the PCH and 2 on ASM1061 PCIe-to-SATA bridge
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@32 PS2, Line 32: - S3 suspend/resume from either Linux or Windows 10. Now it immediately : resumes. That means Super I/O power management is bonkers.
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@36 PS2, Line 36: Booting from the two SATA ports provided by the ASM1061 Same story with Asus P8H61-M PRO
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@38 PS2, Line 38: Internal flashing with flashrom-1.2 (no write permission on BIOS : region). Even with coreboot?
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@40 PS2, Line 40: - The ME on my board. While measuring on the Super I/O pins during S3 : suspend I probably shorted something. Since then the ME has trouble : coming up and the vendor BIOS doesn't work anymore. coreboot works. : I'm now testing with `me_cleaner -S` applied. Tried fresh ME firmware? You can use the Instant Flash image from https://www.asrock.com/mb/Intel/H77%20Pro4-M/index.asp#BIOS as it contains all regions.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 3: H77PRO4_M
Yes. […]
Well, for now it's not a big deal. It's just that the LGA1155 boards are inconsistent with the LGA1150 boards 😄
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... PS2, Line 11: INTEL_INT15 Drop this since no INT15 handler is installed.
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... PS2, Line 29: default "src/mainboard/$(MAINBOARDDIR)/data.vbt" Add an empty line between Kconfig options
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 4: bootblock-y += gpio.c
Build fails when I remove it. It seems to be called in src/southbridge/intel/bd82x6x/early_pch. […]
Ack, I saw. I don't like `early_init` files being built in two stages for that very reason.
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... PS2, Line 1: /* dummy */ just keep it empty
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 11: #include "superio/nuvoton/nct6776/acpi/superio.asl"
I was able to install and use Windows 10 without a change here, but later I will try what you sugges […]
Alright. If Windows booted, this is good enough for now.
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/1/src/mainboard/asrock/h77pro... PS1, Line 70: /* FIXME: Put proper SPD map here. */
Thanks for explaining how to check. Boots with a single DIMM in any slot.
It's the "standard" mapping
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... PS2, Line 13: HDMI3, nit: Which is HDMI, and which is DVI? Feel free to add comments
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45317
to look at the new patch set (#3).
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
mb/asrock: Add ASRock H77 Pro4-M mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM.
The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot.
Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - Rear USB3 ports with reasonable transfer rates - All six SATA ports from the PCH - All two SATA ports from the ASM1061 PCIe-to-SATA bridge - Console output on the serial port of the Super I/O - SeaBIOS 1.14.0 to boot slackware64 - SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS) - External flashing with flashrom-1.2 and a Raspberry Pi 1
WAS working until I changed some things inbetween: - S3 suspend/resume from either Linux or Windows 10. Now it immediately resumes.
Not working: - Booting from the two SATA ports provided by the ASM1061 - Fan control with the NCT6776D Super I/O - Internal flashing with flashrom-1.2 (no write permission on BIOS region). - The ME on my board. While measuring on the Super I/O pins during S3 suspend I probably shorted something. Since then the ME has trouble coming up and the vendor BIOS doesn't work anymore. coreboot works. I'm now testing with `me_cleaner -S` applied.
Untested: - VBT (it is included, though) - Internal USB3 header (2 ports) - SATA 6Gb/s - Rear eSATA connector - Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler michael.buechler@posteo.net --- A src/mainboard/asrock/h77pro4-m/Kconfig A src/mainboard/asrock/h77pro4-m/Kconfig.name A src/mainboard/asrock/h77pro4-m/Makefile.inc A src/mainboard/asrock/h77pro4-m/acpi/ec.asl A src/mainboard/asrock/h77pro4-m/acpi/platform.asl A src/mainboard/asrock/h77pro4-m/acpi/superio.asl A src/mainboard/asrock/h77pro4-m/acpi_tables.c A src/mainboard/asrock/h77pro4-m/board_info.txt A src/mainboard/asrock/h77pro4-m/data.vbt A src/mainboard/asrock/h77pro4-m/devicetree.cb A src/mainboard/asrock/h77pro4-m/dsdt.asl A src/mainboard/asrock/h77pro4-m/early_init.c A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads A src/mainboard/asrock/h77pro4-m/gpio.c A src/mainboard/asrock/h77pro4-m/hda_verb.c 15 files changed, 553 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45317/3
Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 3:
(9 comments)
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@14 PS2, Line 14: Pro4
Pro3
Done
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@19 PS2, Line 19: - PS/2 mouse or keyboard
Both work, only one port?
Should be more clear now. Both mouse and keyboard are tested and work.
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@25 PS2, Line 25: - All eight SATA ports
6 on the PCH and 2 on ASM1061 PCIe-to-SATA bridge
Done
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@38 PS2, Line 38: Internal flashing with flashrom-1.2 (no write permission on BIOS : region).
Even with coreboot?
Yes. I didn't take notes on everything or investigate properly what I'm doing but when I modified these values in the FD at 0x62, 0x66, 0x6a to 0xffff (all of them) I was able to write (flashrom-1.2, booted from coreboot). At some address it failed, though.
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@40 PS2, Line 40: - The ME on my board. While measuring on the Super I/O pins during S3 : suspend I probably shorted something. Since then the ME has trouble : coming up and the vendor BIOS doesn't work anymore. coreboot works. : I'm now testing with `me_cleaner -S` applied.
Tried fresh ME firmware? You can use the Instant Flash image from https://www.asrock. […]
Yes, I tried those (2.00 and Beta 2.10). After the measurement incident I put the original SPI chip with the untouched vendor BIOS back in and it didn't work. I had dropped the chip just before so first I thought some bits had fallen out, but no, that wasn't it :) Another PSU won't help either.
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... PS2, Line 11: INTEL_INT15
Drop this since no INT15 handler is installed.
Done
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... PS2, Line 29: default "src/mainboard/$(MAINBOARDDIR)/data.vbt"
Add an empty line between Kconfig options
Done
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... PS2, Line 1: /* dummy */
just keep it empty
Done
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... File src/mainboard/asrock/h77pro4-m/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/45317/2/src/mainboard/asrock/h77pro... PS2, Line 13: HDMI3,
nit: Which is HDMI, and which is DVI? Feel free to add comments
Easy, I took notes on it anyway
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 3: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@38 PS2, Line 38: Internal flashing with flashrom-1.2 (no write permission on BIOS : region).
Yes. […]
flashrom will fail if it cannot read some region (e.g. the ME region) even if not going to flash it. This is to allow verification and attempt recovery if there are errors. The --noverify-all option (which flashrom should tell you about, if it's not an ancient version) is what you would want to use with a locked ME region.
https://review.coreboot.org/c/coreboot/+/45317/2//COMMIT_MSG@40 PS2, Line 40: - The ME on my board. While measuring on the Super I/O pins during S3 : suspend I probably shorted something. Since then the ME has trouble : coming up and the vendor BIOS doesn't work anymore. coreboot works. : I'm now testing with `me_cleaner -S` applied.
Yes, I tried those (2.00 and Beta 2.10). […]
Ouch.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45317
to look at the new patch set (#4).
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
mb/asrock: Add ASRock H77 Pro4-M mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM.
The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot.
Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - Rear USB3 ports with reasonable transfer rates - Internal USB3 header (2 ports) - All six SATA ports from the PCH - All two SATA ports from the ASM1061 PCIe-to-SATA bridge - Console output on the serial port of the Super I/O - SeaBIOS 1.14.0 to boot slackware64 - SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS) - External flashing with flashrom-1.2 and a Raspberry Pi 1 - S3 suspend/resume from either Linux or Windows 10
Not working: - Booting from the two SATA ports provided by the ASM1061 - Fan control with the NCT6776D Super I/O - Internal flashing with flashrom-1.2 (no write permission on BIOS region).
Untested: - VBT (it is included, though) - SATA 6Gb/s - Rear eSATA connector - Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler michael.buechler@posteo.net --- A src/mainboard/asrock/h77pro4-m/Kconfig A src/mainboard/asrock/h77pro4-m/Kconfig.name A src/mainboard/asrock/h77pro4-m/Makefile.inc A src/mainboard/asrock/h77pro4-m/acpi/ec.asl A src/mainboard/asrock/h77pro4-m/acpi/platform.asl A src/mainboard/asrock/h77pro4-m/acpi/superio.asl A src/mainboard/asrock/h77pro4-m/acpi_tables.c A src/mainboard/asrock/h77pro4-m/board_info.txt A src/mainboard/asrock/h77pro4-m/data.vbt A src/mainboard/asrock/h77pro4-m/devicetree.cb A src/mainboard/asrock/h77pro4-m/dsdt.asl A src/mainboard/asrock/h77pro4-m/early_init.c A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads A src/mainboard/asrock/h77pro4-m/gpio.c A src/mainboard/asrock/h77pro4-m/hda_verb.c 15 files changed, 551 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45317/4
Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4: Alright so the good news first, I was able to fix the board. The new Super I/O wasn't enough, I also replaced Q812, a p-MOSFET that switches off 3.3V to a bunch of components during deep S5. I'm not 100% sure if it was broken or even related to any issues. The total stick through my legs was that some of my SPI flash chips seem to be bad. Only one chip can boot with coreboot or the vendor BIOS, the other two fail somewhat randomly early on. Externally reading them is 100% correct though. Some OTP bits? I didn't investigate any further.
The bad news is that I had to deploy the board in my father's PC so (a) I don't have regular access to test things and (b) his installation of Windows 10, which was originally Windows 7 or even Vista on an ASRock 4CoreDual-SATA2, doesn't come back from S3. I don't have a serial log yet. A clean installation of Windows 10 does resume properly though, as does Linux.
Other than that the board seems to be working nicely so I'm pushing the current state.
Attention is currently required from: Michael Büchler. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 4: Code-Review+1
(12 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45317/comment/fe5cb925_0a7bffbf PS4, Line 30: (needs VGA BIOS) I know Windows 10 works on Sandy/Ivy without a VGA BIOS when:
- libgfxinit sets up a linear "high-resolution" framebuffer - payload is TianoCore - coreboot contains the VBT
https://review.coreboot.org/c/coreboot/+/45317/comment/1707ce1f_ff4971d1 PS4, Line 42: SATA 6Gb/s I imagine this is because none of your SATA drives are 6Gbps-capable?
https://review.coreboot.org/c/coreboot/+/45317/comment/7671353a_6e6d5128 PS4, Line 43: Rear eSATA connector It's multiplexed with the second SATA port of the ASM1061. Looks like the eSATA connector has a SATA_SEL pin, which should activate the multiplexor chip. The SATA_SEL pin is also wired to Super I/O GP23 (which is probably configured as an input and only used so that vendor firmware can read the level of SATA_SEL).
File src/mainboard/asrock/h77pro4-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/45317/comment/14e9e653_705e7a06 PS4, Line 26: config INTEL_GMA_VBT_FILE : string : default "src/mainboard/$(MAINBOARDDIR)/data.vbt" : : config INTEL_GMA_ADD_VBT : bool : default y Remove these and simply select `INTEL_GMA_HAVE_VBT`
File src/mainboard/asrock/h77pro4-m/acpi_tables.c:
PS4: This file can be removed. The GNVS values aren't used.
File src/mainboard/asrock/h77pro4-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45317/comment/d28d89b8_ee516815 PS4, Line 4: 0x0 nit: Use `0` instead of `0x0`
https://review.coreboot.org/c/coreboot/+/45317/comment/d3565fe1_36ac829c PS4, Line 9: 0x0 nit: same
https://review.coreboot.org/c/coreboot/+/45317/comment/ff96e38a_69759b15 PS4, Line 13: 0x0 nit: same
https://review.coreboot.org/c/coreboot/+/45317/comment/dc68d820_40f8ecee PS4, Line 22: register "c2_latency" = "0x0065" Can be removed, it's the default value when unspecified.
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/dc597028_f22c2aa0 PS4, Line 54: /* Configure GPIO7 */ : pnp_set_logical_device(GPIO6789_DEV); : pnp_write_config(GPIO6789_DEV, 0xe0, 0x3f); : pnp_write_config(GPIO6789_DEV, 0xe1, 0x7f); As per the Z77 Pro4-M boardview, these two GPIOs control which of the two CPU fan headers should the Super I/O monitor the speed of. GP76 controls CPU_FAN2 and GP77 controls CPU_FAN1. Each GPIO drives a pair of MOSFETs that connect or isolate the fan header's tachometer signal, and they're active-low (0 -> tachometer connected, 1 -> tachometer isolated/ignored). The values you program here select CPU_FAN1.
Ideally, this would be configurable. At the very least, I'd expand the comment to explain what this GPIO7 configuration is used for.
If you want to test my theory, you can use lm-sensors to check "CPU fan" speed readings for each of these cases:
pnp_write_config(GPIO6789_DEV, 0xe1, 0x3f); /* CPU fan speed would always be 0 */ pnp_write_config(GPIO6789_DEV, 0xe1, 0x7f); /* CPU fan speed reports CPU_FAN1 speed */ pnp_write_config(GPIO6789_DEV, 0xe1, 0xbf); /* CPU fan speed reports CPU_FAN2 speed */
Enabling both CPU_FAN1 and CPU_FAN2 at the same time would merely confuse the Super I/O.
File src/mainboard/asrock/h77pro4-m/gpio.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/925c6e96_e4533b6d PS4, Line 71: .gpio13 = GPIO_INVERT,
Input Inversion (GP_INV[n]) — R/W. This bit only has effect if the corresponding GPIO is used as an input and used by the GPE logic, where the polarity matters. When set to ‘1’, then the GPI is inverted as it is sent to the GPE logic that is using it. This bit has no effect on the value that is reported in the GP_LVL register.
The devicetree doesn't enable GPEs for GPIO13, so the programmed value is irrelevant. Hmmm, now I wonder what this GPIO is used for.
Looking at the Z77 Pro4-M boardview, this GPIO is connected to the PME# signal (pin 65) of the Super I/O. The NCT6776 datasheet says the following about the PME# signal:
The PME# (pin 65) signal is connected to the South Bridge and is used to wake up the system from S1 sleeping states.
One control bit and four registers in the NCT6776F / NCT6776D are associated with the PME function. The control bit is at Logical Device A, CR[F2h], bit[0] and is for enabling or disabling the PME function. If this bit is set to “0”, the NCT6776F / NCT6776D won’t output any PME signal when any of the wake-up events has occurred and is enabled.
Logical Device A, CR[F2h], bit[0] defaults to 0 (Disable PME), and this patch doesn't set it. So, it doesn't matter.
TL;DR: Just leave this as-is. I was curious and dug into why this GPIO uses inversion.
File src/mainboard/asrock/h77pro4-m/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/1277647f_5bfd6498 PS4, Line 6: Realtek nit: Realtek ALC892
Attention is currently required from: Michael Büchler. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45317
to look at the new patch set (#5).
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
mb/asrock: Add ASRock H77 Pro4-M mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM.
The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot.
Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - All rear and internal USB3 ports with reasonable transfer rates - All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) - All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) - SATA at 6 Gb/s - Rear eSATA connector (multiplexed with one ASM1061 port) - Console output on the serial port of the Super I/O - SeaBIOS 1.14.0 to boot slackware64 - SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS) - Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`) - External flashing with flashrom-1.2 and a Raspberry Pi 1 - S3 suspend/resume from either Linux or Windows 10
Not working: - Booting from the two SATA ports provided by the ASM1061 - Fan control with the NCT6776D Super I/O
Untested: - VBT (it is included, though) - Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler michael.buechler@posteo.net --- A src/mainboard/asrock/h77pro4-m/Kconfig A src/mainboard/asrock/h77pro4-m/Kconfig.name A src/mainboard/asrock/h77pro4-m/Makefile.inc A src/mainboard/asrock/h77pro4-m/acpi/ec.asl A src/mainboard/asrock/h77pro4-m/acpi/platform.asl A src/mainboard/asrock/h77pro4-m/acpi/superio.asl A src/mainboard/asrock/h77pro4-m/board_info.txt A src/mainboard/asrock/h77pro4-m/data.vbt A src/mainboard/asrock/h77pro4-m/devicetree.cb A src/mainboard/asrock/h77pro4-m/dsdt.asl A src/mainboard/asrock/h77pro4-m/early_init.c A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads A src/mainboard/asrock/h77pro4-m/gpio.c A src/mainboard/asrock/h77pro4-m/hda_verb.c 14 files changed, 537 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45317/5
Attention is currently required from: Angel Pons. Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 5:
(12 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45317/comment/3400a0d6_b60d3596 PS2, Line 32: - S3 suspend/resume from either Linux or Windows 10. Now it immediately : resumes.
That means Super I/O power management is bonkers.
It came back to its senses. With the soldering inbetween I can't really say what the issue was, but it works again.
Commit Message:
https://review.coreboot.org/c/coreboot/+/45317/comment/76f7e5bb_333fa0de PS4, Line 30: (needs VGA BIOS)
I know Windows 10 works on Sandy/Ivy without a VGA BIOS when: […]
I gave this a try and it works well until Windows 10 installs the graphics drivers, then the display goes black/standby and never comes back until I use the VGA BIOS or a PCIe graphics card. So for now I think the statement still holds.
https://review.coreboot.org/c/coreboot/+/45317/comment/1d29e8fd_213a1df5 PS4, Line 42: SATA 6Gb/s
I imagine this is because none of your SATA drives are 6Gbps-capable?
I have some, but I had not checked if they actually get configured for 6Gbps and show transfer rates >3Gbps. Now I tested it for both controllers (H77 and ASM1061) and it looks OK.
https://review.coreboot.org/c/coreboot/+/45317/comment/a3bd3914_5d61a68f PS4, Line 43: Rear eSATA connector
It's multiplexed with the second SATA port of the ASM1061. […]
Confirmed. Attaching an eSATA drive disconnects the internal drive on the upper of the two ASM1061 ports (SATA3_A1) and clears the bit that corresponds to GP23 in the Super I/O registers. Good to know.. I should add this to the documentation I guess? Thanks for investigating!
File src/mainboard/asrock/h77pro4-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/45317/comment/cf82b5fd_48158c14 PS4, Line 26: config INTEL_GMA_VBT_FILE : string : default "src/mainboard/$(MAINBOARDDIR)/data.vbt" : : config INTEL_GMA_ADD_VBT : bool : default y
Remove these and simply select `INTEL_GMA_HAVE_VBT`
Done
File src/mainboard/asrock/h77pro4-m/acpi_tables.c:
PS4:
This file can be removed. The GNVS values aren't used.
Done
File src/mainboard/asrock/h77pro4-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45317/comment/951ae2ca_543982d2 PS4, Line 4: 0x0
nit: Use `0` instead of `0x0`
Done
https://review.coreboot.org/c/coreboot/+/45317/comment/78378e70_19fe931b PS4, Line 9: 0x0
nit: same
Done
https://review.coreboot.org/c/coreboot/+/45317/comment/4c4b0301_5bc5e911 PS4, Line 13: 0x0
nit: same
Done
https://review.coreboot.org/c/coreboot/+/45317/comment/107834b2_c6761a77 PS4, Line 22: register "c2_latency" = "0x0065"
Can be removed, it's the default value when unspecified.
Done
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/560be341_b7ba908b PS4, Line 54: /* Configure GPIO7 */ : pnp_set_logical_device(GPIO6789_DEV); : pnp_write_config(GPIO6789_DEV, 0xe0, 0x3f); : pnp_write_config(GPIO6789_DEV, 0xe1, 0x7f);
As per the Z77 Pro4-M boardview, these two GPIOs control which of the two CPU fan headers should the […]
Nice, I was able to confirm this by setting these GPIOs from a booted Linux. Setting the GPIO to '0' connects the fan tachometer signal to the Super I/O as you said. Just your example code mixes it up a little. This should be correct: ``` pnp_write_config(GPIO6789_DEV, 0xe1, 0xff); /* CPU fan speed would always be 0 */ pnp_write_config(GPIO6789_DEV, 0xe1, 0x7f); /* CPU fan speed reports CPU_FAN1 speed */ pnp_write_config(GPIO6789_DEV, 0xe1, 0xbf); /* CPU fan speed reports CPU_FAN2 speed */ pnp_write_config(GPIO6789_DEV, 0xe1, 0x3f); /* Both connected, wrong readings if both present */ ``` An easy way to configure this would indeed be nice. Can you suggest something? A value in NVRAM (cmos.layout) seems useful..
File src/mainboard/asrock/h77pro4-m/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/4fb73621_5abda53d PS4, Line 6: Realtek
nit: Realtek ALC892
Done
Attention is currently required from: Angel Pons, Michael Büchler. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 5: Code-Review+1
Attention is currently required from: Angel Pons. Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/45317/comment/ebf1496b_a89bf8a4 PS2, Line 38: Internal flashing with flashrom-1.2 (no write permission on BIOS : region).
flashrom will fail if it cannot read some region (e.g. the ME region) even if not going to flash it. […]
Thanks for clarifiying this. With a closer look at the flashrom output this should have been apparrent. ME region is locked (cannot be read). With `--noverify-all` the bios region can be flashed.
Patchset:
PS5: So what's left?
* NVRAM for config options * Super I/O * there was a suggestion to remove the include of superio.asl * PECI + automatic fan control?! * more?
Attention is currently required from: Angel Pons. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45317
to look at the new patch set (#6).
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
mb/asrock: Add ASRock H77 Pro4-M mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM.
The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot.
Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - All rear and internal USB3 ports with reasonable transfer rates - All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) - All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) - SATA at 6 Gb/s - Rear eSATA connector (multiplexed with one ASM1061 port) - Console output on the serial port of the Super I/O - SeaBIOS 1.14.0 to boot slackware64 - SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS) - Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`) - External flashing with flashrom-1.2 and a Raspberry Pi 1 - S3 suspend/resume from either Linux or Windows 10
Not working: - Booting from the two SATA ports provided by the ASM1061 - Fan control with the NCT6776D Super I/O
Untested: - VBT (it is included, though) - Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler michael.buechler@posteo.net --- A Documentation/mainboard/asrock/h77pro4-m.md M Documentation/mainboard/index.md A src/mainboard/asrock/h77pro4-m/Kconfig A src/mainboard/asrock/h77pro4-m/Kconfig.name A src/mainboard/asrock/h77pro4-m/Makefile.inc A src/mainboard/asrock/h77pro4-m/acpi/ec.asl A src/mainboard/asrock/h77pro4-m/acpi/platform.asl A src/mainboard/asrock/h77pro4-m/acpi/superio.asl A src/mainboard/asrock/h77pro4-m/board_info.txt A src/mainboard/asrock/h77pro4-m/cmos.default A src/mainboard/asrock/h77pro4-m/cmos.layout A src/mainboard/asrock/h77pro4-m/data.vbt A src/mainboard/asrock/h77pro4-m/devicetree.cb A src/mainboard/asrock/h77pro4-m/dsdt.asl A src/mainboard/asrock/h77pro4-m/early_init.c A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads A src/mainboard/asrock/h77pro4-m/gpio.c A src/mainboard/asrock/h77pro4-m/hda_verb.c 18 files changed, 822 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45317/6
Attention is currently required from: Angel Pons. Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 6:
(2 comments)
Patchset:
PS6: I added documentation and a way to configure the fan header for CPUFANIN (see comment below).
I also changed `acpi/superio.asl` to not include the nct6776-specific `superio.asl` anymore. This was suggested to me at some point. A PS/2 keyboard or mouse still works in Linux, but in Windows, only a PS/2 keyboard does, not a mouse. I might never have tested it before the change, though.
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/b7e0a4c3_4473af14 PS4, Line 54: /* Configure GPIO7 */ : pnp_set_logical_device(GPIO6789_DEV); : pnp_write_config(GPIO6789_DEV, 0xe0, 0x3f); : pnp_write_config(GPIO6789_DEV, 0xe1, 0x7f);
Nice, I was able to confirm this by setting these GPIOs from a booted Linux. […]
I copied the CMOS option tables from mb/asus/p8z77-v_lx2 and looked at mb/kontron/986lcd-m/mainboard.c on how to create a new entry and use it.
Without a config in CMOS I chose the default to be CPU_FAN1 - probably the most popular choice.
I tested all combinations and it works as expected.
Attention is currently required from: Michael Büchler. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 6: Code-Review+1
(16 comments)
Patchset:
PS6:
I added documentation and a way to configure the fan header for CPUFANIN (see comment below). […]
I think I suggested this change because Windows hates NCT6776 ACPI
PS6: Just some minor things here and there, and this will be ready to go!
File Documentation/mainboard/asrock/h77pro4-m.md:
https://review.coreboot.org/c/coreboot/+/45317/comment/96452d1d_e30e733b PS6, Line 24: header I'd mention it's RS-232 (and not TTL UART)
https://review.coreboot.org/c/coreboot/+/45317/comment/584b2e3e_cb201570 PS6, Line 45: SATA at 6 Gb/s Doesn't this repeat part of what the two preceding lines say? I'd remove it
https://review.coreboot.org/c/coreboot/+/45317/comment/9d0df447_347f9d96 PS6, Line 147: work, check if your bracket expects a different assignment. I'm worried about people connecting things that doesn't use RS-232 voltages to this header, and frying them. But I wouldn't expect this kind of people to read warnings anyway.
File src/mainboard/asrock/h77pro4-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/45317/comment/70244ac9_b5992129 PS6, Line 22: string Type no longer needed, see CB:56553
https://review.coreboot.org/c/coreboot/+/45317/comment/c7537d84_b0edc725 PS6, Line 26: string Type no longer needed, see CB:56554
File src/mainboard/asrock/h77pro4-m/cmos.layout:
https://review.coreboot.org/c/coreboot/+/45317/comment/470a9438_54d2a0cc PS6, Line 28: cpu_fan_header Since this option is about the tachometer signal source, how about naming it `cpu_fan_tach_src` instead?
File src/mainboard/asrock/h77pro4-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45317/comment/3fe68f8f_41651723 PS6, Line 75: # parallel port Comment seems redundant
File src/mainboard/asrock/h77pro4-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/45317/comment/0922916b_7baa141d PS6, Line 10: /* OEM revision */ This comment comes from autoport, right? I'd remove it.
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/10acf7cb_3943f93c PS4, Line 54: /* Configure GPIO7 */ : pnp_set_logical_device(GPIO6789_DEV); : pnp_write_config(GPIO6789_DEV, 0xe0, 0x3f); : pnp_write_config(GPIO6789_DEV, 0xe1, 0x7f);
I copied the CMOS option tables from mb/asus/p8z77-v_lx2 and looked at mb/kontron/986lcd-m/mainboard […]
Sounds great!
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/47e8df54_d4d28827 PS6, Line 3: #include <bootblock_common.h> : #include <device/pci_ops.h> : #include <device/pnp_ops.h> : #include <northbridge/intel/sandybridge/raminit_native.h> : #include <southbridge/intel/bd82x6x/pch.h> : #include <superio/nuvoton/nct6776/nct6776.h> : #include <superio/nuvoton/common/nuvoton.h> : #include <option.h> nit: maybe order includes alphabetically?
https://review.coreboot.org/c/coreboot/+/45317/comment/cad8d80b_265027e1 PS6, Line 18: #define CPU_FAN_HEADER_NONE 0 : #define CPU_FAN_HEADER_1 1 : #define CPU_FAN_HEADER_2 2 : #define CPU_FAN_HEADER_BOTH 3 nit: Use an enum?
https://review.coreboot.org/c/coreboot/+/45317/comment/9bb02e9b_90208f77 PS6, Line 43: u8 #include <stdint.h>
https://review.coreboot.org/c/coreboot/+/45317/comment/361c9386_e1bcaa79 PS6, Line 73: cpu_fan_header = get_uint_option("cpu_fan_header", CPU_FAN_HEADER_1); : switch (cpu_fan_header) { : case CPU_FAN_HEADER_NONE: : reg = 0xff; : break; : case CPU_FAN_HEADER_1: : reg = 0x7f; : break; : case CPU_FAN_HEADER_2: : reg = 0xbf; : break; : case CPU_FAN_HEADER_BOTH: : reg = 0x3f; : break; : } Idea: place the switch/case statement in a helper function, so that you can replace the assignments and break statements with one return statement:
static u8 get_cpu_fan_header(void) { switch (get_uint_option("cpu_fan_header", CPU_FAN_HEADER_1)) { case CPU_FAN_HEADER_NONE: return 0xff; case CPU_FAN_HEADER_1: default: return 0x7f; case CPU_FAN_HEADER_2: return 0xbf; case CPU_FAN_HEADER_BOTH: return 0x3f; } }
Note that I added a `default:` case. This is to handle the unusual case where `get_uint_option()` returns something other than the defined values (which could only happen if something goes very wrong).
Feel free to pick a different function name. I'm not very inspired today 😄
File src/mainboard/asrock/h77pro4-m/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/2eebf7dd_593a63c2 PS6, Line 32: nit: drop blank line?
Attention is currently required from: Michael Büchler. Hello build bot (Jenkins), Martin Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45317
to look at the new patch set (#7).
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
mb/asrock: Add ASRock H77 Pro4-M mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM.
The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot.
Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - All rear and internal USB3 ports with reasonable transfer rates - All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) - All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) - Rear eSATA connector (multiplexed with one ASM1061 port) - Console output on the serial port of the Super I/O - SeaBIOS 1.14.0 to boot slackware64 - SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS) - Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`) - External flashing with flashrom-1.2 and a Raspberry Pi 1 - S3 suspend/resume from either Linux or Windows 10
Not working: - Booting from the two SATA ports provided by the ASM1061 - Fan control with the NCT6776D Super I/O
Untested: - VBT (it is included, though) - Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler michael.buechler@posteo.net --- A Documentation/mainboard/asrock/h77pro4-m.md M Documentation/mainboard/index.md A src/mainboard/asrock/h77pro4-m/Kconfig A src/mainboard/asrock/h77pro4-m/Kconfig.name A src/mainboard/asrock/h77pro4-m/Makefile.inc A src/mainboard/asrock/h77pro4-m/acpi/ec.asl A src/mainboard/asrock/h77pro4-m/acpi/platform.asl A src/mainboard/asrock/h77pro4-m/acpi/superio.asl A src/mainboard/asrock/h77pro4-m/board_info.txt A src/mainboard/asrock/h77pro4-m/cmos.default A src/mainboard/asrock/h77pro4-m/cmos.layout A src/mainboard/asrock/h77pro4-m/data.vbt A src/mainboard/asrock/h77pro4-m/devicetree.cb A src/mainboard/asrock/h77pro4-m/dsdt.asl A src/mainboard/asrock/h77pro4-m/early_init.c A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads A src/mainboard/asrock/h77pro4-m/gpio.c A src/mainboard/asrock/h77pro4-m/hda_verb.c 18 files changed, 821 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45317/7
Attention is currently required from: Angel Pons. Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 7:
(15 comments)
File Documentation/mainboard/asrock/h77pro4-m.md:
https://review.coreboot.org/c/coreboot/+/45317/comment/8936c0e1_065352fe PS6, Line 24: header
I'd mention it's RS-232 (and not TTL UART)
Done, good point
https://review.coreboot.org/c/coreboot/+/45317/comment/23b4096e_4f87858b PS6, Line 45: SATA at 6 Gb/s
Doesn't this repeat part of what the two preceding lines say? I'd remove it
It meant to reflect that I specifically tested it to work at 6 Gb/s speed, but I guess it's more redundant than informative..
https://review.coreboot.org/c/coreboot/+/45317/comment/4e280851_535b85dd PS6, Line 147: work, check if your bracket expects a different assignment.
I'm worried about people connecting things that doesn't use RS-232 voltages to this header, and fryi […]
We should still try to get to these people.. in this case, putting myself into the mind of an adventurous person who doesn't know RS-232 but wants to find out, I think adding a bit of an explanation helps. I added a sentence that others will probably just read past.
File src/mainboard/asrock/h77pro4-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/45317/comment/ea7f0e85_739d79b8 PS6, Line 22: string
Type no longer needed, see CB:56553
Done
https://review.coreboot.org/c/coreboot/+/45317/comment/c220e8b8_b0eb4269 PS6, Line 26: string
Type no longer needed, see CB:56554
Done
File src/mainboard/asrock/h77pro4-m/cmos.layout:
https://review.coreboot.org/c/coreboot/+/45317/comment/757013b1_f075fc7a PS6, Line 28: cpu_fan_header
Since this option is about the tachometer signal source, how about naming it `cpu_fan_tach_src` inst […]
Yes, it's more specific. The fan will still work even if the header is not set here, so `cpu_fan_header` might be misleading. Thanks.
File src/mainboard/asrock/h77pro4-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45317/comment/3fd14c87_e101c0e9 PS6, Line 75: # parallel port
Comment seems redundant
Done
File src/mainboard/asrock/h77pro4-m/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/45317/comment/2d8bc638_d507a02a PS6, Line 10: /* OEM revision */
This comment comes from autoport, right? I'd remove it.
Yes it does. Done.
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/166a9f5d_682e4ad8 PS6, Line 3: #include <bootblock_common.h> : #include <device/pci_ops.h> : #include <device/pnp_ops.h> : #include <northbridge/intel/sandybridge/raminit_native.h> : #include <southbridge/intel/bd82x6x/pch.h> : #include <superio/nuvoton/nct6776/nct6776.h> : #include <superio/nuvoton/common/nuvoton.h> : #include <option.h>
nit: maybe order includes alphabetically?
The lack of order on these include lines often bothers me but I never thought about a good general rule. Quick research on the internet shows that some people have asked that question before and other people have opinions. There is a Google C++ Style Guide which has a short section on this topic. It also suggests an alphabetical order in this case.
But should one sort by the basename or the full path? Probably the full path..
https://review.coreboot.org/c/coreboot/+/45317/comment/2bfda1ed_ee1e7f0d PS6, Line 18: #define CPU_FAN_HEADER_NONE 0 : #define CPU_FAN_HEADER_1 1 : #define CPU_FAN_HEADER_2 2 : #define CPU_FAN_HEADER_BOTH 3
nit: Use an enum?
Sure. I was pleased to see that using an enum instead of multiple defines doesn't change the final image with BUILD_TIMELESS=1.
https://review.coreboot.org/c/coreboot/+/45317/comment/cc1ff163_8de9b00d PS6, Line 43: u8
#include <stdint. […]
Done
https://review.coreboot.org/c/coreboot/+/45317/comment/88019f1c_76d816f5 PS6, Line 57: // FIXME 0x13,0x14 "Device IRQ Polarity Selection" are set by the vendor BIOS The vendor firmware sets these both to 0xff (default 0x00) but I realized that coreboot seems to do the same. I'll remove it.
https://review.coreboot.org/c/coreboot/+/45317/comment/6703b81f_39c95782 PS6, Line 59: // TODO check if it's okay to have this in devicetree.cb : /* Power RAM in S3 */ : pnp_set_logical_device(ACPI_DEV); : pnp_wr I'm putting a comment here to make sure that I test suspend-to-RAM without this.
This sets the "3VSBSW# enable bit". The vendor firmware doesn't set it. The board uses the active-high "3VSBSW" signal on pin 70 instead of "3VSBSW#" on pin 71 to select +5VSB or +5V on +5V_DUAL. Maybe that's why.
If it turns out to be necessary, should it be set in devicetree.cb instead?
https://review.coreboot.org/c/coreboot/+/45317/comment/e2820d0d_4f1899b8 PS6, Line 73: cpu_fan_header = get_uint_option("cpu_fan_header", CPU_FAN_HEADER_1); : switch (cpu_fan_header) { : case CPU_FAN_HEADER_NONE: : reg = 0xff; : break; : case CPU_FAN_HEADER_1: : reg = 0x7f; : break; : case CPU_FAN_HEADER_2: : reg = 0xbf; : break; : case CPU_FAN_HEADER_BOTH: : reg = 0x3f; : break; : }
Idea: place the switch/case statement in a helper function, so that you can replace the assignments […]
Done. I felt inspired enough to change the function name to `get_cpufanin_gpio_config` because it gets the value to be set on the GPIO register - might not be perfect.
Other than that I rarely write C and I really need this kind of suggestion, thanks :)
Oh also I can't test this change on hardware right away, maybe Sunday though..
File src/mainboard/asrock/h77pro4-m/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/23b82748_ad35151f PS6, Line 32:
nit: drop blank line?
Done
Attention is currently required from: Michael Büchler. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 7: Code-Review+1
(5 comments)
File Documentation/mainboard/asrock/h77pro4-m.md:
https://review.coreboot.org/c/coreboot/+/45317/comment/0e6c1d14_0dd48e9e PS6, Line 147: work, check if your bracket expects a different assignment.
We should still try to get to these people.. […]
Perfect!
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/53206601_25b27613 PS6, Line 3: #include <bootblock_common.h> : #include <device/pci_ops.h> : #include <device/pnp_ops.h> : #include <northbridge/intel/sandybridge/raminit_native.h> : #include <southbridge/intel/bd82x6x/pch.h> : #include <superio/nuvoton/nct6776/nct6776.h> : #include <superio/nuvoton/common/nuvoton.h> : #include <option.h>
The lack of order on these include lines often bothers me but I never thought about a good general r […]
I sort by full path. Anyway, this is just cosmetics
https://review.coreboot.org/c/coreboot/+/45317/comment/3f01e3ef_ce58c099 PS6, Line 59: // TODO check if it's okay to have this in devicetree.cb : /* Power RAM in S3 */ : pnp_set_logical_device(ACPI_DEV); : pnp_wr
I'm putting a comment here to make sure that I test suspend-to-RAM without this. […]
I'm pretty sure it's needed. Setting it in devicetree.cb should work, especially considering it's where LDN 0xa (ACPI) offset 0xf0 is programmed accordingly: https://imgur.com/Dn7kHij.png
https://review.coreboot.org/c/coreboot/+/45317/comment/ce319288_bade10db PS6, Line 73: cpu_fan_header = get_uint_option("cpu_fan_header", CPU_FAN_HEADER_1); : switch (cpu_fan_header) { : case CPU_FAN_HEADER_NONE: : reg = 0xff; : break; : case CPU_FAN_HEADER_1: : reg = 0x7f; : break; : case CPU_FAN_HEADER_2: : reg = 0xbf; : break; : case CPU_FAN_HEADER_BOTH: : reg = 0x3f; : break; : }
Done. […]
Good function name, I like it! I'll let you mark this one as resolved, I'm not sure if you've tested this yet.
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/0128d645_8f19574c PS7, Line 44: /* The tachometer signal that goes to CPUFANIN of the Super I/O is set via : * GPIOs. : * When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected. : * When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected. : * When both are '0' and both fans are connected, wrong readings will : * be reported. */ Please adapt this comment's style: https://doc.coreboot.org/contributing/coding_style.html#commenting
Attention is currently required from: Michael Büchler. Hello build bot (Jenkins), Martin Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45317
to look at the new patch set (#8).
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
mb/asrock: Add ASRock H77 Pro4-M mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM.
The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot.
Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - All rear and internal USB3 ports with reasonable transfer rates - All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) - All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) - Rear eSATA connector (multiplexed with one ASM1061 port) - Console output on the serial port of the Super I/O - SeaBIOS 1.14.0 to boot slackware64 - SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS) - Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`) - External flashing with flashrom-1.2 and a Raspberry Pi 1 - S3 suspend/resume from either Linux or Windows 10
Not working: - Booting from the two SATA ports provided by the ASM1061 - Fan control with the NCT6776D Super I/O
Untested: - VBT (it is included, though) - Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler michael.buechler@posteo.net --- A Documentation/mainboard/asrock/h77pro4-m.md M Documentation/mainboard/index.md A src/mainboard/asrock/h77pro4-m/Kconfig A src/mainboard/asrock/h77pro4-m/Kconfig.name A src/mainboard/asrock/h77pro4-m/Makefile.inc A src/mainboard/asrock/h77pro4-m/acpi/ec.asl A src/mainboard/asrock/h77pro4-m/acpi/platform.asl A src/mainboard/asrock/h77pro4-m/acpi/superio.asl A src/mainboard/asrock/h77pro4-m/board_info.txt A src/mainboard/asrock/h77pro4-m/cmos.default A src/mainboard/asrock/h77pro4-m/cmos.layout A src/mainboard/asrock/h77pro4-m/data.vbt A src/mainboard/asrock/h77pro4-m/devicetree.cb A src/mainboard/asrock/h77pro4-m/dsdt.asl A src/mainboard/asrock/h77pro4-m/early_init.c A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads A src/mainboard/asrock/h77pro4-m/gpio.c A src/mainboard/asrock/h77pro4-m/hda_verb.c 18 files changed, 816 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45317/8
Attention is currently required from: Angel Pons. Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 8:
(4 comments)
Patchset:
PS8: Thanks once again! I also tested a build based on a current master, but it failed to boot. Probably because it was inbetween commit 29c7622 and commit 7d925c5? I had no serial port with me to get any debugging output.
Next test on 19th December. Will it be ready this year? :D
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/bc0bc584_813206e3 PS6, Line 59: // TODO check if it's okay to have this in devicetree.cb : /* Power RAM in S3 */ : pnp_set_logical_device(ACPI_DEV); : pnp_wr
I'm pretty sure it's needed. Setting it in devicetree. […]
First I tested it without these lines here. You're right, it is needed. Without it there is no +5V_DUAL during suspend and the DRAM goes down. I moved this to devicetree.cb and will test it again.
https://review.coreboot.org/c/coreboot/+/45317/comment/90b0609b_f898c561 PS6, Line 73: cpu_fan_header = get_uint_option("cpu_fan_header", CPU_FAN_HEADER_1); : switch (cpu_fan_header) { : case CPU_FAN_HEADER_NONE: : reg = 0xff; : break; : case CPU_FAN_HEADER_1: : reg = 0x7f; : break; : case CPU_FAN_HEADER_2: : reg = 0xbf; : break; : case CPU_FAN_HEADER_BOTH: : reg = 0x3f; : break; : }
Good function name, I like it! I'll let you mark this one as resolved, I'm not sure if you've tested […]
Glad to hear it! I did the test and it still works as expected. I also saw no reason to keep the intermediate variable `reg` so I removed it, I hope that's fine. The resulting binary is identical.
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/bd1ce40a_ce6052e7 PS7, Line 44: /* The tachometer signal that goes to CPUFANIN of the Super I/O is set via : * GPIOs. : * When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected. : * When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected. : * When both are '0' and both fans are connected, wrong readings will : * be reported. */
Please adapt this comment's style: https://doc.coreboot.org/contributing/coding_style. […]
Ha! I was actually looking for this section but I was too impatient to find it. You were referring to the newlines only, not the content, right? I added three of them. One too many?
Attention is currently required from: Michael Büchler. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 8: Code-Review+1
(1 comment)
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/b504ded5_82f1247d PS6, Line 73: cpu_fan_header = get_uint_option("cpu_fan_header", CPU_FAN_HEADER_1); : switch (cpu_fan_header) { : case CPU_FAN_HEADER_NONE: : reg = 0xff; : break; : case CPU_FAN_HEADER_1: : reg = 0x7f; : break; : case CPU_FAN_HEADER_2: : reg = 0xbf; : break; : case CPU_FAN_HEADER_BOTH: : reg = 0x3f; : break; : }
Glad to hear it! I did the test and it still works as expected. […]
Perfect!
Attention is currently required from: Michael Büchler. Hello build bot (Jenkins), Martin Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45317
to look at the new patch set (#9).
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
mb/asrock: Add ASRock H77 Pro4-M mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM.
The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot.
Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - All rear and internal USB3 ports with reasonable transfer rates - All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) - All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) - Rear eSATA connector (multiplexed with one ASM1061 port) - Console output on the serial port of the Super I/O - SeaBIOS 1.14.0 to boot slackware64 - SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS) - Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`) - External flashing with flashrom-1.2 and a Raspberry Pi 1 - S3 suspend/resume from either Linux or Windows 10
Not working: - Booting from the two SATA ports provided by the ASM1061 - Fan control with the NCT6776D Super I/O
Untested: - VBT (it is included, though) - Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler michael.buechler@posteo.net --- A Documentation/mainboard/asrock/h77pro4-m.md M Documentation/mainboard/index.md A src/mainboard/asrock/h77pro4-m/Kconfig A src/mainboard/asrock/h77pro4-m/Kconfig.name A src/mainboard/asrock/h77pro4-m/Makefile.inc A src/mainboard/asrock/h77pro4-m/acpi/ec.asl A src/mainboard/asrock/h77pro4-m/acpi/platform.asl A src/mainboard/asrock/h77pro4-m/acpi/superio.asl A src/mainboard/asrock/h77pro4-m/board_info.txt A src/mainboard/asrock/h77pro4-m/cmos.default A src/mainboard/asrock/h77pro4-m/cmos.layout A src/mainboard/asrock/h77pro4-m/data.vbt A src/mainboard/asrock/h77pro4-m/devicetree.cb A src/mainboard/asrock/h77pro4-m/dsdt.asl A src/mainboard/asrock/h77pro4-m/early_init.c A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads A src/mainboard/asrock/h77pro4-m/gpio.c A src/mainboard/asrock/h77pro4-m/hda_verb.c 18 files changed, 825 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45317/9
Attention is currently required from: Angel Pons. Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 9:
(2 comments)
Patchset:
PS9: Now works after rebasing.
* SeaBIOS changed to 1.15.0 * added a note about the eSATA port to the doc (unnecessary?) * 3VSBSW# setting moved from early_init.c to devicetree.cb
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/b9afd51c_3183ba65 PS6, Line 59: // TODO check if it's okay to have this in devicetree.cb : /* Power RAM in S3 */ : pnp_set_logical_device(ACPI_DEV); : pnp_wr
First I tested it without these lines here. You're right, it is needed. […]
Moved to devicetree.cb, resuming from suspend works.
Attention is currently required from: Michael Büchler. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 9: Code-Review+1
(1 comment)
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/419feb07_ea7b16cc PS7, Line 44: /* The tachometer signal that goes to CPUFANIN of the Super I/O is set via : * GPIOs. : * When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected. : * When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected. : * When both are '0' and both fans are connected, wrong readings will : * be reported. */
Ha! I was actually looking for this section but I was too impatient to find it. […]
I was referring to the comment format. One option:
/* * The tachometer signal that goes to CPUFANIN of the Super I/O is set via * GPIOs. * When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected. * When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected. * When both are '0' and both fans are connected, wrong readings will * be reported. */
Attention is currently required from: Michael Büchler. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 9:
(4 comments)
File src/mainboard/asrock/h77pro4-m/Kconfig:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135918): https://review.coreboot.org/c/coreboot/+/45317/comment/f73b0709_ee22121b PS9, Line 18: select SUPERIO_NUVOTON_NCT6776 'SUPERIO' may be misspelled - perhaps ''?
File src/mainboard/asrock/h77pro4-m/devicetree.cb:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135918): https://review.coreboot.org/c/coreboot/+/45317/comment/ffd4db64_e40ec589 PS9, Line 72: chip superio/nuvoton/nct6776 'superio' may be misspelled - perhaps ''?
File src/mainboard/asrock/h77pro4-m/early_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135918): https://review.coreboot.org/c/coreboot/+/45317/comment/f6029f80_5ed68d6f PS9, Line 11: #include <superio/nuvoton/common/nuvoton.h> 'superio' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135918): https://review.coreboot.org/c/coreboot/+/45317/comment/febe5869_4ed83704 PS9, Line 12: #include <superio/nuvoton/nct6776/nct6776.h> 'superio' may be misspelled - perhaps ''?
Attention is currently required from: Angel Pons. Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/064a2c30_94e690fd PS7, Line 44: /* The tachometer signal that goes to CPUFANIN of the Super I/O is set via : * GPIOs. : * When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected. : * When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected. : * When both are '0' and both fans are connected, wrong readings will : * be reported. */
I was referring to the comment format. One option: […]
So.. the current state with my update is okay? :D compared to your suggestion there is one more newline that I think improves readability a little..
Attention is currently required from: Michael Büchler. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/asrock/h77pro4-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/45317/comment/a46d3a9b_d0c82772 PS7, Line 44: /* The tachometer signal that goes to CPUFANIN of the Super I/O is set via : * GPIOs. : * When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected. : * When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected. : * When both are '0' and both fans are connected, wrong readings will : * be reported. */
So.. […]
Perfect
Attention is currently required from: Michael Büchler. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 9:
(2 comments)
Patchset:
PS9: Just one last thing!
File Documentation/mainboard/asrock/h77pro4-m.md:
https://review.coreboot.org/c/coreboot/+/45317/comment/835d25fc_d63662da PS9, Line 59: Fan control with the NCT6776D Super I/O nit: *Automatic* fan control (linux' fancontrol/pwmconfig should work)
Attention is currently required from: Michael Büchler. Hello build bot (Jenkins), Martin Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45317
to look at the new patch set (#10).
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
mb/asrock: Add ASRock H77 Pro4-M mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM.
The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot.
Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - All rear and internal USB3 ports with reasonable transfer rates - All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) - All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) - Rear eSATA connector (multiplexed with one ASM1061 port) - Console output on the serial port of the Super I/O - SeaBIOS 1.15.0 to boot slackware64 - SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS) - Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`) - External flashing with flashrom-1.2 and a Raspberry Pi 1 - S3 suspend/resume from either Linux or Windows 10
Not working: - Booting from the two SATA ports provided by the ASM1061 - Automatic fan control with the NCT6776D Super I/O
Untested: - VBT (it is included, though) - Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler michael.buechler@posteo.net --- A Documentation/mainboard/asrock/h77pro4-m.md M Documentation/mainboard/index.md A src/mainboard/asrock/h77pro4-m/Kconfig A src/mainboard/asrock/h77pro4-m/Kconfig.name A src/mainboard/asrock/h77pro4-m/Makefile.inc A src/mainboard/asrock/h77pro4-m/acpi/ec.asl A src/mainboard/asrock/h77pro4-m/acpi/platform.asl A src/mainboard/asrock/h77pro4-m/acpi/superio.asl A src/mainboard/asrock/h77pro4-m/board_info.txt A src/mainboard/asrock/h77pro4-m/cmos.default A src/mainboard/asrock/h77pro4-m/cmos.layout A src/mainboard/asrock/h77pro4-m/data.vbt A src/mainboard/asrock/h77pro4-m/devicetree.cb A src/mainboard/asrock/h77pro4-m/dsdt.asl A src/mainboard/asrock/h77pro4-m/early_init.c A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads A src/mainboard/asrock/h77pro4-m/gpio.c A src/mainboard/asrock/h77pro4-m/hda_verb.c 18 files changed, 826 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45317/10
Attention is currently required from: Michael Büchler. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 10:
(4 comments)
File src/mainboard/asrock/h77pro4-m/Kconfig:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135933): https://review.coreboot.org/c/coreboot/+/45317/comment/ba88f5c6_50bbbea5 PS10, Line 18: select SUPERIO_NUVOTON_NCT6776 'SUPERIO' may be misspelled - perhaps ''?
File src/mainboard/asrock/h77pro4-m/devicetree.cb:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135933): https://review.coreboot.org/c/coreboot/+/45317/comment/5aeb1c5f_25c7ffda PS10, Line 72: chip superio/nuvoton/nct6776 'superio' may be misspelled - perhaps ''?
File src/mainboard/asrock/h77pro4-m/early_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135933): https://review.coreboot.org/c/coreboot/+/45317/comment/16214de5_20a9dddd PS10, Line 11: #include <superio/nuvoton/common/nuvoton.h> 'superio' may be misspelled - perhaps ''?
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135933): https://review.coreboot.org/c/coreboot/+/45317/comment/fb6b683f_8bb5c354 PS10, Line 12: #include <superio/nuvoton/nct6776/nct6776.h> 'superio' may be misspelled - perhaps ''?
Attention is currently required from: Angel Pons. Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 10:
(1 comment)
File Documentation/mainboard/asrock/h77pro4-m.md:
https://review.coreboot.org/c/coreboot/+/45317/comment/69898b62_cfbbd600 PS9, Line 59: Fan control with the NCT6776D Super I/O
nit: *Automatic* fan control (linux' fancontrol/pwmconfig should work)
oh yes this could have been misleading. It is currently set up with SpeedFan on Windows 10. Works well.
Attention is currently required from: Michael Büchler. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
Patch Set 10: Code-Review+2
(1 comment)
File Documentation/mainboard/asrock/h77pro4-m.md:
https://review.coreboot.org/c/coreboot/+/45317/comment/a51f33d3_50095de3 PS9, Line 59: Fan control with the NCT6776D Super I/O
oh yes this could have been misleading. It is currently set up with SpeedFan on Windows 10. […]
Good to know! BTW, CB:42136 implements the necessary stuff to configure the HWM, but it currently lacks a proper configuration system (I just hardcoded the settings I like on the Asrock B85M Pro4). I have no idea when I'll finish it, though.
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45317 )
Change subject: mb/asrock: Add ASRock H77 Pro4-M mainboard ......................................................................
mb/asrock: Add ASRock H77 Pro4-M mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM.
The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot.
Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - All rear and internal USB3 ports with reasonable transfer rates - All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) - All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) - Rear eSATA connector (multiplexed with one ASM1061 port) - Console output on the serial port of the Super I/O - SeaBIOS 1.15.0 to boot slackware64 - SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS) - Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`) - External flashing with flashrom-1.2 and a Raspberry Pi 1 - S3 suspend/resume from either Linux or Windows 10
Not working: - Booting from the two SATA ports provided by the ASM1061 - Automatic fan control with the NCT6776D Super I/O
Untested: - VBT (it is included, though) - Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler michael.buechler@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/45317 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- A Documentation/mainboard/asrock/h77pro4-m.md M Documentation/mainboard/index.md A src/mainboard/asrock/h77pro4-m/Kconfig A src/mainboard/asrock/h77pro4-m/Kconfig.name A src/mainboard/asrock/h77pro4-m/Makefile.inc A src/mainboard/asrock/h77pro4-m/acpi/ec.asl A src/mainboard/asrock/h77pro4-m/acpi/platform.asl A src/mainboard/asrock/h77pro4-m/acpi/superio.asl A src/mainboard/asrock/h77pro4-m/board_info.txt A src/mainboard/asrock/h77pro4-m/cmos.default A src/mainboard/asrock/h77pro4-m/cmos.layout A src/mainboard/asrock/h77pro4-m/data.vbt A src/mainboard/asrock/h77pro4-m/devicetree.cb A src/mainboard/asrock/h77pro4-m/dsdt.asl A src/mainboard/asrock/h77pro4-m/early_init.c A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads A src/mainboard/asrock/h77pro4-m/gpio.c A src/mainboard/asrock/h77pro4-m/hda_verb.c 18 files changed, 826 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/Documentation/mainboard/asrock/h77pro4-m.md b/Documentation/mainboard/asrock/h77pro4-m.md new file mode 100644 index 0000000..45c603d --- /dev/null +++ b/Documentation/mainboard/asrock/h77pro4-m.md @@ -0,0 +1,174 @@ +# ASRock H77 Pro4-M + +The ASRock H77 Pro4-M is a microATX-sized desktop board for Intel Sandy +Bridge and Ivy Bridge CPUs. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | Intel H77 (bd82x6x) | ++------------------+--------------------------------------------------+ +| CPU socket | LGA 1155 | ++------------------+--------------------------------------------------+ +| RAM | 4 x DDR3-1600 | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6776 | ++------------------+--------------------------------------------------+ +| Audio | Realtek ALC892 | ++------------------+--------------------------------------------------+ +| Network | Realtek RTL8111E | ++------------------+--------------------------------------------------+ +| Serial | Internal header (RS-232) | ++------------------+--------------------------------------------------+ +``` + +## Status + +Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12 +(linux-4.19.50). + +### Working + +- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) +- Native RAM initialization with four DIMMs +- PS/2 combined port (mouse or keyboard) +- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) +- PCIe graphics in the PEG slot +- All three additional PCIe slots +- All rear and internal USB2 ports +- All rear and internal USB3 ports +- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) +- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) +- Rear eSATA connector (multiplexed with one ASM1061 port) +- Gigabit Ethernet +- Console output on the serial port +- SeaBIOS 1.14.0 and 1.15.0 to boot Windows 10 (needs VGA BIOS) and Linux via +extlinux +- Internal flashing with flashrom-1.2, see +[Internal Programming](#internal-programming) +- External flashing with flashrom-1.2 and a Raspberry Pi 1 +- S3 suspend/resume from either Linux or Windows 10 +- Poweroff + +### Not working + +- Booting from the two SATA ports provided by the ASM1061 +- Automatic fan control with the NCT6776D Super I/O + +### Untested + +- EHCI debug +- S/PDIF audio +- Other audio jacks than the green one, and the front panel header +- Parallel port +- Infrared/CIR +- Wakeup from anything but the power button + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | yes | ++---------------------+------------+ +| Model | W25Q64.V | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | DIP-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +The flash is divided into the following regions, as obtained with +`ifdtool -f rom.layout backup.rom`: +``` +00000000:00000fff fd +00200000:007fffff bios +00001000:001fffff me +``` + +### Internal programming + +The main SPI flash can be accessed using flashrom. By default, only +the BIOS region of the flash is writable. If you wish to change any +other region (Management Engine or flash descriptor), then an external +programmer is required. + +The following command may be used to flash coreboot: + +``` +$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom +``` + +The use of `--noverify-all` is required since the Management Engine +region is not readable even by the host. + +```eval_rst +In addition to the information here, please see the +:doc:`../../flash_tutorial/index`. +``` + +## Hardware monitoring and fan control + +There are two fan headers for the CPU cooler, CPU_FAN1 and CPU_FAN2. They share +a single fan tachometer input on the Super I/O while some dedicated logic +selects which one is allowed to reach it. Two GPIO pins on the Super I/O are +used to control that logic. The firmware has to set them; coreboot selects +CPU_FAN1 by default, but the user can change that setting if it was built with +CONFIG_USE_OPTION_TABLE: + +``` +$ sudo nvramtool -e cpu_fan_header +[..] +$ sudo nvramtool -w cpu_fan_header=CPU_FAN2 +$ sudo nvramtool -w cpu_fan_header=None +$ sudo nvramtool -w cpu_fan_header=Both +``` + +The setting will take effect after a reboot. Selecting and connecting both fan +headers is possible but the Super I/O will report wrong fan speeds. + +Currently there is no automatic, OS-independent fan control, but a software +like `fancontrol` from the lm-sensors package can be used instead. + +## Serial port header + +Serial port 1, provided by the Super I/O, is exposed on a pin header. The +RS-232 signals are assigned to the header so that its pin numbers map directly +to the pin numbers of a DE-9 connector. If your serial port doesn't seem to +work, check if your bracket expects a different assignment. Also don't try to +connect it directly to a device that operates at TTL levels - it would need a +level converter like a MAX232. + +Here is a top view of the serial port header found on this board: + + +---+---+ + N/C | | 9 | RI -> pin 9 + +---+---+ + Pin 8 <- CTS | 8 | 7 | RTS -> pin 7 + +---+---+ + Pin 6 <- DSR | 6 | 5 | GND -> pin 5 + +---+---+ + Pin 4 <- DTR | 4 | 3 | TxD -> pin 3 + +---+---+ + Pin 2 <- RxD | 2 | 1 | DCD -> pin 1 + +---+---+ + +## eSATA + +The eSATA port on the rear I/O panel and the internal connector SATA3_A1 share +the same controller port on the ASM1061. Attaching an eSATA drive causes a +multiplexer chip to disconnect the internal port from the SATA controller and +connect the eSATA port instead. This can be seen on GP23 of the Super I/O +GPIOs: it is '0' when something is connected to the eSATA port and '1' +otherwise. diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 0d5ec5f..fc602de 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -11,6 +11,7 @@
## ASRock
+- [H77 Pro4-M](asrock/h77pro4-m.md) - [H81M-HDS](asrock/h81m-hds.md) - [H110M-DVS](asrock/h110m-dvs.md)
diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig b/src/mainboard/asrock/h77pro4-m/Kconfig new file mode 100644 index 0000000..50bf86c --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_H77PRO4_M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASPM_BLACKLIST + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_NUVOTON_NCT6776 + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + default "asrock/h77pro4-m" + +config MAINBOARD_PART_NUMBER + default "H77 Pro4-M" + +endif diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig.name b/src/mainboard/asrock/h77pro4-m/Kconfig.name new file mode 100644 index 0000000..03873b9 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_H77PRO4_M + bool "H77 Pro4-M" diff --git a/src/mainboard/asrock/h77pro4-m/Makefile.inc b/src/mainboard/asrock/h77pro4-m/Makefile.inc new file mode 100644 index 0000000..a0d1155 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/h77pro4-m/acpi/ec.asl b/src/mainboard/asrock/h77pro4-m/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi/ec.asl diff --git a/src/mainboard/asrock/h77pro4-m/acpi/platform.asl b/src/mainboard/asrock/h77pro4-m/acpi/platform.asl new file mode 100644 index 0000000..146be65 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/h77pro4-m/acpi/superio.asl b/src/mainboard/asrock/h77pro4-m/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asrock/h77pro4-m/board_info.txt b/src/mainboard/asrock/h77pro4-m/board_info.txt new file mode 100644 index 0000000..5f86088 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/H77%20Pro4-M/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asrock/h77pro4-m/cmos.default b/src/mainboard/asrock/h77pro4-m/cmos.default new file mode 100644 index 0000000..23386fb --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +debug_level=Debug +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI +gfx_uma_size=64M +cpu_fan_tach_src=CPU_FAN1 diff --git a/src/mainboard/asrock/h77pro4-m/cmos.layout b/src/mainboard/asrock/h77pro4-m/cmos.layout new file mode 100644 index 0000000..ac88ee9 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/cmos.layout @@ -0,0 +1,96 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi + +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode + +# coreboot config options: northbridge +416 5 e 6 gfx_uma_size + +# coreboot config options: mainboard-specific +421 2 e 7 cpu_fan_tach_src + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +2 0 Fallback +2 1 Normal + +# debug_level +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +# power_on_after_fail +4 0 Disable +4 1 Enable +4 2 Keep + +# sata_mode +5 0 AHCI +5 1 Compatible +5 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M + +# cpu_fan_header (select which header provides the tachometer +# signal to the Super I/O on its CPUFANIN input) +7 0 None +7 1 CPU_FAN1 +7 2 CPU_FAN2 +7 3 Both + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/asrock/h77pro4-m/data.vbt b/src/mainboard/asrock/h77pro4-m/data.vbt new file mode 100644 index 0000000..52a8268 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/data.vbt Binary files differ diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb new file mode 100644 index 0000000..86468c1 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x1849 0x0100 + end + device pci 01.0 on end # PEG - slot "PCIE1" + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0102 + end + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1849 0x1e31 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0x1e3a + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x1e2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x8892 + end + device pci 1c.0 on # PCIe Port #1 - slot "PCIE4", 4 lanes + subsystemid 0x1849 0x1e10 + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 - slot "PCIE2", 1 lane + subsystemid 0x1849 0x1e18 + end + device pci 1c.5 on # PCIe Port #6 - RTL8111E GbE + subsystemid 0x1849 0x1e1a + end + device pci 1c.6 on # PCIe Port #7 - slot "PCIE3", 1 lane + subsystemid 0x1849 0x1e16 + end + device pci 1c.7 on # PCIe Port #8 - ASM1061 SATA Controller + subsystemid 0x1849 0x1e1e + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x1e26 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1e4a + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT1 + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 on # GPIO base + io 0x60 = 0x0 + irq 0xf0 = 0x3e # + GPIO1 direction + irq 0xf1 = 0xde # + GPIO1 value + end + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 on # GPIO2 + irq 0xe0 = 0xff # + GPIO2 direction + irq 0xe1 = 0x0c # + GPIO2 value + end + device pnp 2e.309 on # GPIO3 + irq 0xe4 = 0xf7 # + GPIO3 direction + irq 0xe5 = 0x08 # + GPIO3 value + end + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on end # GPIO7 + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + enable 3VSBSW# + irq 0xf0 = 0x20 # + pin 70 = 3VSBSW + end + device pnp 2e.b on # HWM, front panel LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO Push-Pull or Open-drain + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep Sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA (AHCI) + subsystemid 0x1849 0x1e02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x1e22 + end + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/h77pro4-m/dsdt.asl b/src/mainboard/asrock/h77pro4-m/dsdt.asl new file mode 100644 index 0000000..33cd0e5 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c new file mode 100644 index 0000000..48024cb --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/early_init.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <option.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define GPIO6789_DEV PNP_DEV(0x2e, NCT6776_GPIO6789_V) + +/* As defined in cmos.layout */ +enum cpu_fan_tach_src { + CPU_FAN_HEADER_NONE, + CPU_FAN_HEADER_1, + CPU_FAN_HEADER_2, + CPU_FAN_HEADER_BOTH +}; + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 0, 6 }, +}; + +/* + * The tachometer signal that goes to CPUFANIN of the Super I/O is set via + * GPIOs. + * + * When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected. + * When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected. + * When both are '0' and both fans are connected, wrong readings will + * be reported. + */ +static u8 get_cpufanin_gpio_config(void) +{ + switch (get_uint_option("cpu_fan_tach_src", CPU_FAN_HEADER_1)) { + case CPU_FAN_HEADER_NONE: + return 0xff; + case CPU_FAN_HEADER_1: + default: + return 0x7f; + case CPU_FAN_HEADER_2: + return 0xbf; + case CPU_FAN_HEADER_BOTH: + return 0x3f; + } +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Configure Super I/O pins */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xc0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x08); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + + /* GP77 and GP76 are outputs. They set the tachometer input on CPUFANIN. */ + pnp_set_logical_device(GPIO6789_DEV); + pnp_write_config(GPIO6789_DEV, 0xe0, 0x3f); + pnp_write_config(GPIO6789_DEV, 0xe1, get_cpufanin_gpio_config()); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads b/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads new file mode 100644 index 0000000..b05255d --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D connector + HDMI3, -- HDMI connector + Analog, -- D-Sub connector + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/h77pro4-m/gpio.c b/src/mainboard/asrock/h77pro4-m/gpio.c new file mode 100644 index 0000000..84f4564 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/gpio.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/h77pro4-m/hda_verb.c b/src/mainboard/asrock/h77pro4-m/hda_verb.c new file mode 100644 index 0000000..51133e7 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/hda_verb.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek ALC892 */ + 0x18498892, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18498892), + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19950), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214120), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES;
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