Change in ...coreboot[master]: soc/intel/denverton_ns: Fix missing tsc_freq_mhz()

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30763

Change subject: soc/intel/denverton_ns: Fix missing tsc_freq_mhz()
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soc/intel/denverton_ns: Fix missing tsc_freq_mhz()

It was relying on bad weak implementation for postcar
and verstage.

Change-Id: I5a520e0166198c0565349c164f143f4a43649861
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/denverton_ns/Makefile.inc
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/30763/1

diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc
index c024c3a..e9d5022 100644
--- a/src/soc/intel/denverton_ns/Makefile.inc
+++ b/src/soc/intel/denverton_ns/Makefile.inc
@@ -31,6 +31,7 @@

postcar-y += memmap.c
 postcar-y += spi.c
+postcar-y += tsc_freq.c
 postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c

romstage-y += memmap.c
@@ -80,6 +81,7 @@
 verstage-y += memmap.c
 verstage-y += reset.c
 verstage-y += spi.c
+verstage-y += tsc_freq.c
 verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c

CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include