the following patch was just integrated into master: commit aff502e87ae57fa2dc09367d00f143b6befb9530 Author: fdurairx felixx.durairaj@intel.com Date: Fri Aug 21 15:36:53 2015 -0700
soc/braswell: Fix DSP clock
The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL.
Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams hannah.williams@intel.com Original-Reviewed-by: Aaron Durbin adurbin@chromium.org
Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj felixx.durairaj@intel.com Reviewed-on: https://review.coreboot.org/12732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth martinroth@google.com
See https://review.coreboot.org/12732 for details.
-gerrit