Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12302
-gerrit
commit 0104fa64d6bd5e26c2baceb73354e47975d59b1c Author: Denis 'GNUtoo' Carikli GNUtoo@no-log.org Date: Thu Jul 30 19:41:57 2015 +0200
mainboard/asus: F2A85-M PRO: switch superIO
Change-Id: Ifa799b5e66ef4b93d464bfeccca27165e82b966b Signed-off-by: Denis 'GNUtoo' Carikli GNUtoo@no-log.org --- src/mainboard/asus/f2a85-m_pro/Kconfig | 2 +- src/mainboard/asus/f2a85-m_pro/devicetree.cb | 50 ++-------- src/mainboard/asus/f2a85-m_pro/romstage.c | 140 ++++++++++++++++++++++++++- 3 files changed, 147 insertions(+), 45 deletions(-)
diff --git a/src/mainboard/asus/f2a85-m_pro/Kconfig b/src/mainboard/asus/f2a85-m_pro/Kconfig index b437ed6..4353444 100644 --- a/src/mainboard/asus/f2a85-m_pro/Kconfig +++ b/src/mainboard/asus/f2a85-m_pro/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES - select SUPERIO_ITE_IT8728F + select SUPERIO_NUVOTON_NCT6779D select BOARD_ROMSIZE_KB_8192 select GFXUMA select HUDSON_DISABLE_IMC diff --git a/src/mainboard/asus/f2a85-m_pro/devicetree.cb b/src/mainboard/asus/f2a85-m_pro/devicetree.cb index 4562557..bde400e 100644 --- a/src/mainboard/asus/f2a85-m_pro/devicetree.cb +++ b/src/mainboard/asus/f2a85-m_pro/devicetree.cb @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2015 Denis 'GNUtoo' Carikli gnutoo@no-log.org # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -56,56 +57,19 @@ chip northbridge/amd/agesa/family15tn/root_complex chip drivers/generic/generic #dimm 1 device i2c 51 on end # 7-bit SPD address end - end # SM + end # SMBUS device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - register hwm_ctl_register = "0xc0" - register hwm_main_ctl_register = "0x33" - register hwm_adc_temp_chan_en_reg = "0x38" - register hwm_fan1_ctl_pwm = "0x00" - register hwm_fan2_ctl_pwm = "0x00" - register hwm_fan3_ctl_pwm = "0x00" - - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 + chip superio/nuvoton/nct6779d + device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Env Controller - io 0x60 = 0x290 - io 0x62 = 0x220 - irq 0x70 = 0 + device pnp 2e.a on # ACPI + irq 0xe7 = 0x10 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x228 #SMI - io 0x62 = 0x300 #Simple I/O - io 0x64 = 0x238 #Phony resource IT8603E does not have it - irq 0x70 = 0 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8728f + end end #device pci 14.3 # LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 diff --git a/src/mainboard/asus/f2a85-m_pro/romstage.c b/src/mainboard/asus/f2a85-m_pro/romstage.c index 0062c87..feeec61 100644 --- a/src/mainboard/asus/f2a85-m_pro/romstage.c +++ b/src/mainboard/asus/f2a85-m_pro/romstage.c @@ -1 +1,139 @@ -#include "../f2a85-m/romstage.c" +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Rudolf Marek r.marek@assembler.cz + * Copyright (C) 2015 Denis 'GNUtoo' Carikli gnutoo@no-log.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/amd/agesa/agesawrapper.h> + +#include <arch/acpi.h> +#include <arch/cpu.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/car.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pnp_def.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <southbridge/amd/agesa/hudson/smbus.h> +#include <stdint.h> +#include <string.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define MMIO_NON_POSTED_START 0xfed00000 +#define MMIO_NON_POSTED_END 0xfedfffff +#define SB_MMIO 0xFED80000 +#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + u8 byte; + device_t dev; + +#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) + hudson_pci_port80(); +#endif +#if IS_ENABLED(CONFIG_POST_DEVICE_LPC) + hudson_lpc_port80(); +#endif + + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + post_code(0x30); + // TODO: SB SuperIO init ? + + post_code(0x31); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* turn on secondary smbus at b20 */ + outb(0x28, 0xcd6); + byte = inb(0xcd7); + byte |= 1; + outb(byte, 0xcd7); + + /* set DDR3 voltage */ + byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; + + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) + do_smbus_write_byte(0xb20, 0x15, 0x3, byte); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + agesawrapper_amdinitreset(); + post_code(0x39); + + agesawrapper_amdinitearly(); + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + post_code(0x41); + agesawrapper_amdinitenv(); + disable_cache_as_ram(); + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + amd_initcpuio(); + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +}
-
Stefan Reinauer