Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39176 )
Change subject: mb/**/dsdt.asl: Remove outdated sleepstates.asl comment ......................................................................
mb/**/dsdt.asl: Remove outdated sleepstates.asl comment
Previously, each Intel chipset had its own sleepstates.asl file. However, this is no longer the case, so drop these comments.
This follows commit 408d1dac9e23250c0e485bbf934771f769b717c1.
Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/volteer/dsdt.asl M src/mainboard/intel/jasperlake_rvp/dsdt.asl M src/mainboard/intel/tglrvp/dsdt.asl 4 files changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39176/1
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 4134b03..45a1486 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -38,7 +38,6 @@ /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
- /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index e4bbe90..f62780b 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -47,6 +47,5 @@ #include <ec/google/chromeec/acpi/ec.asl> }
- // Chipset specific sleep states #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index 8788a1f..4b9a696 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -58,7 +58,6 @@ } #endif
- /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Mainboard specific */ diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index a17f597..8236ccb 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -58,7 +58,6 @@ } #endif
- /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Mainboard specific */
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39176 )
Change subject: mb/**/dsdt.asl: Remove outdated sleepstates.asl comment ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39176 )
Change subject: mb/**/dsdt.asl: Remove outdated sleepstates.asl comment ......................................................................
mb/**/dsdt.asl: Remove outdated sleepstates.asl comment
Previously, each Intel chipset had its own sleepstates.asl file. However, this is no longer the case, so drop these comments.
This follows commit 408d1dac9e23250c0e485bbf934771f769b717c1.
Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39176 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/volteer/dsdt.asl M src/mainboard/intel/jasperlake_rvp/dsdt.asl M src/mainboard/intel/tglrvp/dsdt.asl 4 files changed, 0 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 4134b03..45a1486 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -38,7 +38,6 @@ /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
- /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index e4bbe90..f62780b 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -47,6 +47,5 @@ #include <ec/google/chromeec/acpi/ec.asl> }
- // Chipset specific sleep states #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index 8788a1f..4b9a696 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -58,7 +58,6 @@ } #endif
- /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Mainboard specific */ diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index a17f597..8236ccb 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -58,7 +58,6 @@ } #endif
- /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Mainboard specific */
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39176 )
Change subject: mb/**/dsdt.asl: Remove outdated sleepstates.asl comment ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1011 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1010 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1009
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Nico Huber (Code Review)
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Patrick Georgi (Code Review)