New patch to review for coreboot: northbridge/intel/i945: Remouve commented code

[HAOUAS Elyes]

HAOUAS Elyes ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16876

-gerrit

commit 003271dedb24f250051ecd5c2aa242ba57d98b6a
Author: Elyes HAOUAS 
Date:   Tue Oct 4 19:39:36 2016 +0200

northbridge/intel/i945: Remouve commented code

Change-Id: Ie915a4879c5d6e4472c1ffe86fbd370cbe754cb7
    Signed-off-by: Elyes HAOUAS 
---
 src/northbridge/intel/i945/acpi/i945.asl | 30 ------------------------------
 src/northbridge/intel/i945/early_init.c  |  5 -----
 src/northbridge/intel/i945/raminit.c     | 32 --------------------------------
 3 files changed, 67 deletions(-)

diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl
index 5a93238..478290d 100644
--- a/src/northbridge/intel/i945/acpi/i945.asl
+++ b/src/northbridge/intel/i945/acpi/i945.asl
@@ -42,18 +42,6 @@ Device (PDRC)
    Name (_HID, EISAID("PNP0C02"))
    Name (_UID, 1)

-	// This does not seem to work correctly yet - set values statically for
-	// now.
-
-	//Name (PDRS, ResourceTemplate() {
-	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
-	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
-	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
-	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
-	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
-	//	Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
-	//})
-
    Name (PDRS, ResourceTemplate() {
    	Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
    	Memory32Fixed(ReadWrite, DEFAULT_MCHBAR,   0x00004000)
@@ -68,24 +56,6 @@ Device (PDRC)
    // Current Resource Settings
    Method (_CRS, 0, Serialized)
    {
-		//CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
-		//ShiftLeft(_SB.PCI0.LPCB.RCBA, 14, RBR0)
-
-		//CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
-		//ShiftLeft(_SB.PCI0.MCHC.MHBR, 14, MBR0)
-
-		//CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
-		//ShiftLeft(_SB.PCI0.MCHC.DMBR, 12, DBR0)
-
-		//CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
-		//ShiftLeft(_SB.PCI0.MCHC.EPBR, 12, EBR0)
-
-		//CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
-		//ShiftLeft(_SB.PCI0.MCHC.PXBR, 26, PBR0)
-
-		//CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
-		//ShiftLeft(0x10000000, _SB.PCI0.MCHC.PXSZ, PSZ0)
-
    	Return(PDRS)
    }
 }
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 4373167..7e980a3 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -863,11 +863,6 @@ static void ich7_setup_pci_express(void)

/* Initialize slot power limit for root ports */
    pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060);
-#if 0
-	pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0);
-	pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0);
-#endif
-
    pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000);
 }

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 0b9e95c..2988af0 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -208,19 +208,6 @@ static int sdram_capabilities_enhanced_addressing_xor(void)
    return (!reg8);
 }

-// TODO check if we ever need this function
-#if 0
-static int sdram_capabilities_MEM4G_disable(void)
-{
-	u8 reg8;
-
-	reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
-	reg8 &= (1 << 0);
-
-	return (reg8 != 0);
-}
-#endif
-
 #define GFX_FREQUENCY_CAP_166MHZ	0x04
 #define GFX_FREQUENCY_CAP_200MHZ	0x03
 #define GFX_FREQUENCY_CAP_250MHZ	0x02
@@ -1520,13 +1507,6 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
    if (sysinfo->interleaved)
    	cum1 = 0;

-#if 0
-	/* Exception: Channel 1 is not populated. C1DRB stays zero */
-	if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
-			sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED)
-		cum1 = 0;
-#endif
-
    for (i = 0; i < 2 * DIMM_SOCKETS; i++) {
    	cum1 += sysinfo->banksize[i + 4];
    	MCHBAR8(C1DRB0+i) = cum1;
@@ -2520,11 +2500,7 @@ static void sdram_power_management(struct sys_info *sysinfo)
    }
    MCHBAR16(CPCTL) = reg16;

-#if 0
-	if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
-#else
    if (i945_silicon_revision() != 0) {
-#endif
    	switch (sysinfo->fsb_frequency) {
    	case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
    	case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
@@ -2560,14 +2536,6 @@ static void sdram_power_management(struct sys_info *sysinfo)
    	MCHBAR32(ECO) |= (1 << 16);
    }

-#if 0
-
-	if (i945_silicon_revision() == 0) {
-		MCHBAR32(FSBPMC3) &= ~(1 << 29);
-	} else {
-		MCHBAR32(FSBPMC3) |= (1 << 29);
-	}
-#endif
    MCHBAR32(FSBPMC3) &= ~(1 << 29);

MCHBAR32(FSBPMC3) |= (1 << 21);