Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21498
Change subject: amd/stoneyridge: Convert MP init to mp_init_with_smm ......................................................................
amd/stoneyridge: Convert MP init to mp_init_with_smm
Change the Stoney Ridge SOC to a more modern method for setting up the multiple cores.
Add a new cpu.c file for most of the processor initiliazation. Build mp_ops with the necessary callbacks. Note also that this patch removes cpu_bus_scan. Rather than manually find CPUs and add them to the devicetree, allow this to be done automatically in the generic mp_init.c file.
SMM information is left blank in mp_ops to avoid having mp_init.c install a handler at this time. A later patch will add TSEG SMM capabilities for the APU.
Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/chip.c A src/soc/amd/stoneyridge/cpu.c A src/soc/amd/stoneyridge/include/soc/cpu.h M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/northbridge.c 7 files changed, 88 insertions(+), 83 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/21498/1
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 1e13cc0..f708750 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -49,6 +49,8 @@ select SOC_AMD_COMMON_BLOCK_CAR select C_ENVIRONMENT_BOOTBLOCK select BOOTBLOCK_CONSOLE + select RELOCATABLE_MODULES + select PARALLEL_MP
config VBOOT select AMDFW_OUTSIDE_CBFS diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index b6669f1..07c14ce 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -61,6 +61,7 @@ verstage-y += tsc_freq.c
ramstage-y += chip.c +ramstage-y += cpu.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += fixme.c diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 14f76b7..325d2ea 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -18,20 +18,16 @@ #include <cpu/cpu.h> #include <device/device.h> #include <device/pci.h> -#include <soc/southbridge.h> +#include <soc/cpu.h> #include <soc/northbridge.h> - -static void cpu_bus_init(device_t dev) -{ - initialize_cpus(dev->link_list); -} +#include <soc/southbridge.h>
struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = &cpu_bus_init, - .scan_bus = cpu_bus_scan, + .init = stoney_init_cpus, + .scan_bus = NULL, .acpi_fill_ssdt_generator = generate_cpu_entries, };
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c new file mode 100644 index 0000000..22e1a03 --- /dev/null +++ b/src/soc/amd/stoneyridge/cpu.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <chip.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/lapic.h> +#include <cpu/amd/mtrr.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/pci.h> +#include <soc/pci_devs.h> +#include <soc/cpu.h> +#include <soc/northbridge.h> +#include <soc/southbridge.h> +#include <console/console.h> +#include <cpu/amd/amdfam15.h> +#include <smp/node.h> + +/* + * Do essential initialization tasks before APs can be fired up - + * + * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This + * creates the MTRR solution that the APs will use. Otherwise APs will try to + * apply the incomplete solution as the BSP is calculating it. + */ +static void pre_mp_init(void) +{ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_cpu_count(void) +{ + device_t nb = dev_find_slot(0, HT_DEVFN); + return (pci_read_config16(nb, D18F0_CPU_CNT) & 0xf) + 1; +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, +}; + +void stoney_init_cpus(struct device *dev) +{ + /* Clear for take-off */ + if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + printk(BIOS_ERR, "MP initialization failure.\n"); +} diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h new file mode 100644 index 0000000..029d0a6 --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define D18F0_NODE_ID 0x60 +#define D18F0_CPU_CNT 0x62 + +void stoney_init_cpus(struct device *dev); diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 13d7d36..4f8707c 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -20,7 +20,6 @@ #include <arch/io.h> #include <device/device.h>
-void cpu_bus_scan(device_t dev); void domain_enable_resources(device_t dev); void domain_read_resources(device_t dev); void domain_set_resources(device_t dev); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 739b979..ef075b6 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -503,80 +503,6 @@ reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB); }
-void cpu_bus_scan(device_t dev) -{ - struct bus *cpu_bus; - device_t cpu; - device_t cdb_dev; - device_t dev_mc; - int j; - int core_max; - int core_nums; - int siblings; - int family; - int enable_node; - u32 lapicid_start; - u32 apic_id; - u32 pccount; - - - dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); - if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, - CONFIG_CDB); - die(""); - } - - /* Get max and actual number of cores */ - pccount = cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT); - core_max = 1 << ((pccount >> 12) & 0xf); - core_nums = (pccount & 0xF); - - family = (cpuid_eax(1) >> 20) & 0xff; - - cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 5)); - siblings = pci_read_config32(cdb_dev, 0x84) & 0xff; - - printk(BIOS_SPEW, "%s family%xh, core_max=%d, core_nums=%d," - " siblings=%d\n", dev_path(cdb_dev), 0x0f + family, - core_max, core_nums, siblings); - - /* - * APIC ID calucation is tightly coupled with AGESA v5 code. - * This calculation MUST match the assignment calculation done - * in LocalApicInitializationAtEarly() function. - * And reference GetLocalApicIdForCore() - * - * Apply apic enumeration rules - * For systems with >= 16 APICs, put the IO-APICs at 0..n and - * put the local-APICs at m..z - * - * This is needed because many IO-APIC devices only have 4 bits - * for their APIC id and therefore must reside at 0..15 - */ - - /* - * While the above statement is true, we know some things about - * this silicon. It is an SOC and can't have >= 16 APICs, but - * we will start numbering at 0x10. We also know there is only - * on physical node (module in AMD speak). - */ - - lapicid_start = 0x10; /* Get this from devicetree? see comment above. */ - enable_node = cdb_dev->enabled; - cpu_bus = dev->link_list; - - for (j = 0 ; j <= siblings ; j++) { - apic_id = lapicid_start + j; - printk(BIOS_SPEW, "lapicid_start 0x%x, core 0x%x," - " apicid=0x%x\n", lapicid_start, j, apic_id); - - cpu = add_cpu_device(cpu_bus, apic_id, enable_node); - if (cpu) - amd_cpu_topology(cpu, 1, j); - } -} - /********************************************************************* * Change the vendor / device IDs to match the generic VBIOS header. * *********************************************************************/
-
Marshall Dawson (Code Review)