Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23475
Change subject: cpu/intel/car: Cache the whole ROM_SIZE ......................................................................
cpu/intel/car: Cache the whole ROM_SIZE
This removes the need to have a the akward placement of romstage in cbfs, while providing a small speed boost with mrc.cache (measured 6ms on Sandy Bridge)
Change-Id: If6943634bce1ef1cb119b000d091b5bee007db6e Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/car/Kconfig M src/cpu/intel/car/cache_as_ram.S M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/Kconfig 4 files changed, 7 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/23475/1
diff --git a/src/cpu/intel/car/Kconfig b/src/cpu/intel/car/Kconfig index 2e190ea..7823604 100644 --- a/src/cpu/intel/car/Kconfig +++ b/src/cpu/intel/car/Kconfig @@ -14,6 +14,7 @@
config CPU_INTEL_COMMON_CAR bool + select NO_FIXED_XIP_ROM_SIZE
if CPU_INTEL_COMMON_CAR
diff --git a/src/cpu/intel/car/cache_as_ram.S b/src/cpu/intel/car/cache_as_ram.S index 8f91dc7..cf73dd9 100644 --- a/src/cpu/intel/car/cache_as_ram.S +++ b/src/cpu/intel/car/cache_as_ram.S @@ -26,11 +26,6 @@ (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-/* Cache 4GB - MRC_SIZE_KB for MRC */ -#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) -#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) -#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) - #define NoEvictMod_MSR 0x2e0 #define MSR_BBL_CR_CTL3 0x11e
@@ -202,6 +197,7 @@ orl $CR0_CacheDisable, %eax movl %eax, %cr0
+ post_code(0x27) /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx @@ -209,29 +205,18 @@ * IMPORTANT: The following calculation _must_ be done at runtime. See * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + movl $(-CACHE_ROM_SIZE), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl %esi, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $CACHE_ROM_SIZE, %eax + dec %eax + not %eax + orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
- post_code(0x27) -#if CONFIG_CACHE_MRC_SIZE_KB - /* Enable caching for RAM init code to run faster */ - movl $MTRR_PHYS_BASE(2), %ecx - movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - movl $MTRR_PHYS_MASK(2), %ecx - movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax - movl %esi, %edx - wrmsr -#endif - post_code(0x28) /* Enable cache. */ movl %cr0, %eax diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 7639b60..cf26d05 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -29,10 +29,6 @@ string default "cpu/intel/model_206ax/bootblock.c"
-config XIP_ROM_SIZE - hex - default 0x20000 if USE_NATIVE_RAMINIT - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 043e8de..3fc0277 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -71,10 +71,6 @@ string default "8086,0106"
-config CACHE_MRC_SIZE_KB - int - default 512 - config SANDYBRIDGE_IVYBRIDGE_LVDS def_bool n select VGA
-
Arthur Heymans (Code Review)