Change in coreboot[master]: mb/google/brya/variants/primus: disable LTR for PCIe-eMMC bridge

[Casper Chang (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Hello build bot (Jenkins), Tim Wawrzynczak,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/58831

to look at the new patch set (#2).

Change subject: mb/google/brya/variants/primus: disable LTR for PCIe-eMMC bridge
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mb/google/brya/variants/primus: disable LTR for PCIe-eMMC bridge

disable LTR for PCIe-eMMC bridge

BUG=b:204469567
TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed

Signed-off-by: Casper Chang 
Change-Id: I7236fc7f3318d07f0d9e9d9da7cd463ef3dde1a0
---
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus/overridetree.cb
2 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/58831/2