Change in coreboot[master]: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"

[Vaibhav Shankar (Code Review)]

Attention is currently required from: Bora Guvendik,  Felix Singer, Lijian Zhao, Shaunak Saha, Nico Huber, Martin Roth, Michael Niewöhner, Tim Wawrzynczak, Aaron Durbin, Patrick Rudolph.
Vaibhav Shankar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56662 )

Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
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Patch Set 1:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/56662/comment/8313eb9c_9943c8d1 
PS1, Line 14:
> How was this tested? Does S0ix still work?

S0ix is enabled by default on all recent chromeOs platfroms. You can check the S0ix entry and exit counts from sysfs- PMC core driver

Patchset:

PS1:
> So, the previous values were for Cannon Lake, while the previous ones are Coffee Lake. […]

The cannon lake support was dropped. If you are using Coffe lake, then you might have to use board- skylake values becaue its based out of 14nm.

reference to previous IRTL values(14nm)- 
https://github.com/coreboot/coreboot/blob/master/src/soc/intel/skylake/cpu.c

Why are we modfying cannonlake values ?