Patch set updated for coreboot: 7bd463d southbridge: Don't hide pointers behind typedefs
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7169
-gerrit
commit 7bd463d9171701d562f00367dac6e11ceaa66d58 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Thu Oct 23 02:09:00 2014 +1100
southbridge: Don't hide pointers behind typedefs
Unfortunately coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs:
* 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t'
Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer type exclusively.
Change-Id: Id6c221cc36a2b89db7b11796d947136bac76e565 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/northbridge/via/cx700/lpc.c | 8 ++++---- src/northbridge/via/vx800/lpc.c | 6 +++--- src/northbridge/via/vx900/lpc.c | 14 +++++++------- src/southbridge/amd/agesa/hudson/lpc.c | 12 ++++++------ src/southbridge/amd/agesa/hudson/spi.c | 2 +- src/southbridge/amd/amd8111/lpc.c | 4 ++-- src/southbridge/amd/cimx/sb700/early.c | 6 +++--- src/southbridge/amd/cimx/sb700/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb700/lpc.h | 6 +++--- src/southbridge/amd/cimx/sb800/early.c | 2 +- src/southbridge/amd/cimx/sb800/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb800/lpc.h | 6 +++--- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/cimx/sb900/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb900/lpc.h | 6 +++--- src/southbridge/amd/sb600/early_setup.c | 14 +++++++------- src/southbridge/amd/sb600/lpc.c | 12 ++++++------ src/southbridge/amd/sb600/sata.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 18 +++++++++--------- src/southbridge/amd/sb700/lpc.c | 12 ++++++------ src/southbridge/amd/sb700/sata.c | 2 +- src/southbridge/amd/sb800/lpc.c | 12 ++++++------ src/southbridge/amd/sb800/sata.c | 2 +- src/southbridge/broadcom/bcm5780/nic.c | 2 +- src/southbridge/broadcom/bcm5780/pcix.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++--- src/southbridge/broadcom/bcm5785/bcm5785.h | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 10 +++++----- src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +- src/southbridge/broadcom/bcm5785/ide.c | 4 ++-- src/southbridge/broadcom/bcm5785/lpc.c | 12 ++++++------ src/southbridge/broadcom/bcm5785/sata.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 14 +++++++------- src/southbridge/broadcom/bcm5785/usb.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 10 +++++----- src/southbridge/intel/bd82x6x/lpc.c | 18 +++++++++--------- src/southbridge/intel/bd82x6x/me.c | 14 +++++++------- src/southbridge/intel/bd82x6x/sata.c | 4 ++-- src/southbridge/intel/common/spi.c | 2 +- src/southbridge/intel/esb6300/lpc.c | 22 +++++++++++----------- src/southbridge/intel/esb6300/sata.c | 2 +- src/southbridge/intel/fsp_bd82x6x/lpc.c | 16 ++++++++-------- src/southbridge/intel/fsp_bd82x6x/me.c | 14 +++++++------- src/southbridge/intel/fsp_bd82x6x/sata.c | 4 ++-- src/southbridge/intel/fsp_rangeley/lpc.c | 16 ++++++++-------- src/southbridge/intel/fsp_rangeley/sata.c | 4 ++-- src/southbridge/intel/fsp_rangeley/spi.c | 2 +- src/southbridge/intel/i3100/lpc.c | 22 +++++++++++----------- src/southbridge/intel/i3100/sata.c | 2 +- src/southbridge/intel/i82801ax/lpc.c | 10 +++++----- src/southbridge/intel/i82801bx/lpc.c | 10 +++++----- src/southbridge/intel/i82801cx/lpc.c | 2 +- src/southbridge/intel/i82801dx/lpc.c | 10 +++++----- src/southbridge/intel/i82801ex/lpc.c | 22 +++++++++++----------- src/southbridge/intel/i82801gx/lpc.c | 16 ++++++++-------- src/southbridge/intel/i82801gx/sata.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 14 +++++++------- src/southbridge/intel/i82801ix/sata.c | 8 ++++---- src/southbridge/intel/ibexpeak/lpc.c | 18 +++++++++--------- src/southbridge/intel/ibexpeak/me.c | 14 +++++++------- src/southbridge/intel/ibexpeak/sata.c | 4 ++-- src/southbridge/intel/lynxpoint/lpc.c | 26 +++++++++++++------------- src/southbridge/intel/lynxpoint/sata.c | 4 ++-- src/southbridge/intel/sch/lpc.c | 8 ++++---- src/southbridge/nvidia/ck804/ck804.c | 10 +++++----- src/southbridge/nvidia/ck804/lpc.c | 18 +++++++++--------- src/southbridge/nvidia/ck804/smbus.c | 8 ++++---- src/southbridge/nvidia/mcp55/azalia.c | 2 +- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 14 +++++++------- src/southbridge/nvidia/mcp55/mcp55.h | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 12 ++++++------ src/southbridge/sis/sis966/early_ctrl.c | 2 +- src/southbridge/sis/sis966/lpc.c | 18 +++++++++--------- src/southbridge/sis/sis966/sata.c | 2 +- src/southbridge/via/vt8231/early_serial.c | 2 +- src/southbridge/via/vt8231/lpc.c | 2 +- src/southbridge/via/vt8235/lpc.c | 6 +++--- src/southbridge/via/vt8237r/lpc.c | 8 ++++---- src/southbridge/via/vt8237r/sata.c | 2 +- src/southbridge/via/vt82c686/early_serial.c | 4 ++-- 81 files changed, 329 insertions(+), 329 deletions(-)
diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 1e6d2ce..db810d2 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -80,7 +80,7 @@ static void pci_routing_fixup(struct device *dev) * can't figure out how to do !!!! */
-static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -232,7 +232,7 @@ static void cx700_set_lpc_registers(struct device *dev)
}
-static void cx700_read_resources(device_t dev) +static void cx700_read_resources(struct device *dev) { struct resource *res;
@@ -254,7 +254,7 @@ static void cx700_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void cx700_set_resources(device_t dev) +static void cx700_set_resources(struct device *dev) { struct resource *resource; resource = find_resource(dev, 1); @@ -262,7 +262,7 @@ static void cx700_set_resources(device_t dev) pci_dev_set_resources(dev); }
-static void cx700_enable_resources(device_t dev) +static void cx700_enable_resources(struct device *dev) { /* Enable SuperIO decoding */ pci_dev_enable_resources(dev); diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index c2a8a1d..ca9bfc2 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -103,7 +103,7 @@ static void pci_routing_fixup(struct device *dev) printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__); }
-static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { u16 tmp; /* Debounce LID and PWRBTN# Inputs for 16ms. */ @@ -300,7 +300,7 @@ static void vx800_sb_init(struct device *dev)
/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this device has a resource to set - so set a dummy one */ -static void vx800_read_resources(device_t dev) +static void vx800_read_resources(struct device *dev) {
struct resource *resource; @@ -313,7 +313,7 @@ static void vx800_read_resources(device_t dev) resource->base = 0x2e; }
-static void vx800_set_resources(device_t dev) +static void vx800_set_resources(struct device *dev) { struct resource *resource; resource = find_resource(dev, 1); diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index ac5e4c8..f22cee5 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -50,7 +50,7 @@ * it will work, but perhaps this should be more configurable. */
-static void vx900_lpc_misc_stuff(device_t dev) +static void vx900_lpc_misc_stuff(struct device *dev) { char extint; u8 val; @@ -74,7 +74,7 @@ static void vx900_lpc_misc_stuff(device_t dev) } }
-static void vx900_lpc_dma_setup(device_t dev) +static void vx900_lpc_dma_setup(struct device *dev) { /* These are the steps recommended by VIA in order to get DMA running */
@@ -107,12 +107,12 @@ static void vx900_lpc_dma_setup(device_t dev) * We are assuming this is called before the drivers/generic/ioapic code, * which should be the case if devicetree.cb is set up properly. */ -static void vx900_lpc_ioapic_setup(device_t dev) +static void vx900_lpc_ioapic_setup(struct device *dev) { /* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb * If it's not, then the generic ioapic driver will not set it up * correctly, and the MP table will not be correctly generated */ - device_t ioapic; + struct device *ioapic; for (ioapic = dev->next; ioapic; ioapic = ioapic->next) { if (ioapic->path.type == DEVICE_PATH_IOAPIC) break; @@ -154,7 +154,7 @@ static void vx900_lpc_ioapic_setup(device_t dev) pci_mod_config8(dev, 0x58, 0, 1 << 6); }
-static void vx900_lpc_interrupt_stuff(device_t dev) +static void vx900_lpc_interrupt_stuff(struct device *dev) { /* Enable setting trigger mode through 0x4d0, and 0x4d1 ports * And enable I/O recovery time */ @@ -180,7 +180,7 @@ static void vx900_lpc_interrupt_stuff(device_t dev) vx900_lpc_ioapic_setup(dev); }
-static void vx900_lpc_init(device_t dev) +static void vx900_lpc_init(struct device *dev) { vx900_lpc_interrupt_stuff(dev); vx900_lpc_misc_stuff(dev); @@ -204,7 +204,7 @@ static const struct pci_driver lpc_driver __pci_driver = { #if CONFIG_PIRQ_ROUTE void pirq_assign_irqs(const u8 * pirq) { - device_t lpc; + struct device *lpc;
lpc = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_LPC, 0); diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 1f60bc4..3b0c90d 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -31,11 +31,11 @@ #include <arch/ioapic.h> #include "hudson.h"
-static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev;
/* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -80,7 +80,7 @@ static void lpc_init(device_t dev) cmos_init(0); }
-static void hudson_lpc_read_resources(device_t dev) +static void hudson_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -128,7 +128,7 @@ static void hudson_lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -static void hudson_lpc_enable_childrens_resources(device_t dev) +static void hudson_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -168,7 +168,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev) reg_var[0] = pci_read_config16(dev, 0x64);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -307,7 +307,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); }
-static void hudson_lpc_enable_resources(device_t dev) +static void hudson_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); hudson_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index bbf6dd3..ce22d34 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -86,7 +86,7 @@ static void execute_command(void)
void spi_init(void) { - device_t dev; + struct device * dev;
dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 718b40b..d8fb2e7 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -86,7 +86,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); }
-static void amd8111_lpc_read_resources(device_t dev) +static void amd8111_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -112,7 +112,7 @@ static void amd8111_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 6dc4ff4..b606352 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -34,7 +34,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev;
printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( @@ -69,7 +69,7 @@ void sb_Poweron_Init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8;
//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -83,7 +83,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8;
//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 5d05762..3b4a40a 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -38,7 +38,7 @@ void backup_top_of_ram(uint64_t ramtop) } }
-void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res;
@@ -92,7 +92,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -104,7 +104,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h index b30f247..7d1874f 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.h +++ b/src/southbridge/amd/cimx/sb700/lpc.h @@ -25,8 +25,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000
-void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev);
#endif diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40648ed..0341567 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -33,7 +33,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev;
printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 519e3c1..4663c9f 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -26,7 +26,7 @@ #include <arch/io.h> #include <cbmem.h>
-void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res;
@@ -80,7 +80,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -92,7 +92,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 8a657d8..032db06 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -25,8 +25,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000
-void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev);
#endif diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index f38e691..86e4f89 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -53,7 +53,7 @@ static void execute_command(void)
void spi_init() { - device_t dev; + struct device * dev;
dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index ce1be11..5a56b49 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -23,7 +23,7 @@ #include <arch/ioapic.h>
-void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res;
@@ -77,7 +77,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -89,7 +89,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h index 66f3ccd..fe2f84b 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.h +++ b/src/southbridge/amd/cimx/sb900/lpc.h @@ -24,8 +24,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000
-void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev);
#endif diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index b6611f6..e412217 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -40,7 +40,7 @@ static u8 pmio_read(u8 reg) /* RPR 2.1: Get SB ASIC Revision. */ static u8 get_sb600_revision(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) { @@ -67,7 +67,7 @@ static void sb600_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -106,7 +106,7 @@ static void sb600_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev;
/* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -196,7 +196,7 @@ void soft_reset(void) void sb600_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev;
/* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -241,7 +241,7 @@ void sb600_pci_port80(void) void sb600_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32;
/* Enable LPC controller */ @@ -260,7 +260,7 @@ void sb600_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb600_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte;
printk(BIOS_INFO, "sb600_devices_por_init()\n"); @@ -520,7 +520,7 @@ static void sb600_pmio_por_init(void) */ static void sb600_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte;
/* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index d8e63b5..1a1fab7 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -33,11 +33,11 @@ #include <cpu/amd/powernow.h> #include "sb600.h"
-static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev;
/* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -66,7 +66,7 @@ static void lpc_init(device_t dev) cmos_check_update_date(RTC_HAS_ALTCENTURY); }
-static void sb600_lpc_read_resources(device_t dev) +static void sb600_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -102,7 +102,7 @@ static void sb600_lpc_read_resources(device_t dev) * @param dev the device whos children's resources are to be enabled * */ -static void sb600_lpc_enable_childrens_resources(device_t dev) +static void sb600_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -114,7 +114,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -213,7 +213,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); }
-static void sb600_lpc_enable_resources(device_t dev) +static void sb600_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sb600_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c index a17aab8..b965bb9 100644 --- a/src/southbridge/amd/sb600/sata.c +++ b/src/southbridge/amd/sb600/sata.c @@ -70,7 +70,7 @@ static void sata_init(struct device *dev) struct southbridge_ati_sb600_config *conf; conf = dev->chip_info;
- device_t sm_dev; + struct device *sm_dev; /* SATA SMBus Disable */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index b7a5e77..90dbfa8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -79,7 +79,7 @@ static void sb700_acpi_init(void) /* RPR 2.28: Get SB ASIC Revision. */ static u8 set_sb700_revision(void) { - device_t dev; + pci_devfn_t dev; u8 rev_id, enable_14Mhz, byte; u8 rev = 0;
@@ -136,7 +136,7 @@ void sb7xx_51xx_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -195,7 +195,7 @@ void sb7xx_51xx_lpc_init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8;
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -208,7 +208,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8;
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -221,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index) /* what is its usage? */ u32 __attribute__ ((weak)) get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev;
/* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -290,7 +290,7 @@ void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) void sb7xx_51xx_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev;
/* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -335,7 +335,7 @@ void sb7xx_51xx_pci_port80(void) void sb7xx_51xx_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32;
/* Enable LPC controller */ @@ -354,7 +354,7 @@ void sb7xx_51xx_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb700_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 u32 dword; @@ -607,7 +607,7 @@ static void sb700_pmio_por_init(void) */ static void sb700_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte;
/* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 173de83..c266402 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -40,11 +40,11 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; }
-static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev;
/* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -104,7 +104,7 @@ void backup_top_of_ram(uint64_t ramtop) } }
-static void sb700_lpc_read_resources(device_t dev) +static void sb700_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -151,7 +151,7 @@ static void sb700_lpc_set_resources(struct device *dev) * @param dev the device whose children's resources are to be enabled * */ -static void sb700_lpc_enable_childrens_resources(device_t dev) +static void sb700_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -163,7 +163,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -262,7 +262,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); }
-static void sb700_lpc_enable_resources(device_t dev) +static void sb700_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sb700_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index c0e3c0f..1a7410b 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -86,7 +86,7 @@ static void sata_init(struct device *dev) u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; int i, j;
- device_t sm_dev; + struct device *sm_dev; /* SATA SMBus Disable */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 7a4dd83..143e717 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -28,11 +28,11 @@ #include <arch/io.h> #include "sb800.h"
-static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte; u32 dword; - device_t sm_dev; + struct device *sm_dev;
/* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -70,7 +70,7 @@ static void lpc_init(device_t dev) cmos_check_update_date(RTC_HAS_ALTCENTURY); }
-static void sb800_lpc_read_resources(device_t dev) +static void sb800_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -118,7 +118,7 @@ static void sb800_lpc_set_resources(struct device *dev) * @param dev the device whos children's resources are to be enabled * */ -static void sb800_lpc_enable_childrens_resources(device_t dev) +static void sb800_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -130,7 +130,7 @@ static void sb800_lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled @@ -229,7 +229,7 @@ static void sb800_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); }
-static void sb800_lpc_enable_resources(device_t dev) +static void sb800_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sb800_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c index 5ac6144..c592298 100644 --- a/src/southbridge/amd/sb800/sata.c +++ b/src/southbridge/amd/sb800/sata.c @@ -89,7 +89,7 @@ static void sata_init(struct device *dev) struct southbridge_ati_sb800_config *conf; conf = dev->chip_info;
- device_t sm_dev; + struct device *sm_dev; /* SATA SMBus Disable */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index df59fdc..5fd56dd 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h>
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c index 92a3547..96d0ace 100644 --- a/src/southbridge/broadcom/bcm5780/pcix.c +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h>
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 1675097..822b3ba 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -24,10 +24,10 @@ #include <device/pci_ids.h> #include "bcm5785.h"
-void bcm5785_enable(device_t dev) +void bcm5785_enable(struct device * dev) { - device_t sb_pci_main_dev; - device_t bus_dev; + struct device * sb_pci_main_dev; + struct device * bus_dev; // unsigned index;
/* See if we are on the behind the pcix bridge */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index bc3280f..5eb2f05 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -24,7 +24,7 @@ #include "chip.h"
#ifndef __PRE_RAM__ -void bcm5785_enable(device_t dev); +void bcm5785_enable(struct device * dev); #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..fe0fded 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -24,7 +24,7 @@ static void bcm5785_enable_lpc(void) { uint8_t byte; - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
@@ -43,7 +43,7 @@ static void bcm5785_enable_lpc(void)
static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old;
@@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void)
unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
/* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. @@ -134,7 +134,7 @@ void soft_reset(void)
static void bcm5785_enable_msg(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; uint8_t byte; @@ -162,7 +162,7 @@ static void bcm5785_early_setup(void) { uint8_t byte; uint32_t dword; - device_t dev; + pci_devfn_t dev;
//F0 // enable device on bcm5785 at first diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 38e58f8..200da09 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -24,7 +24,7 @@
static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
if (dev == PCI_DEV_INVALID) { diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 3426a2c..948fef0 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> #include "bcm5785.h"
-static void bcm5785_ide_read_resources(device_t dev) +static void bcm5785_ide_read_resources(struct device * dev) { /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -40,7 +40,7 @@ static void ide_init(struct device *dev) { }
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index af79892..35173d3 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -30,7 +30,7 @@ #include <arch/ioapic.h> #include "bcm5785.h"
-static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { /* Initialize the real time clock */ cmos_init(0); @@ -39,7 +39,7 @@ static void lpc_init(device_t dev) isa_dma_init(); }
-static void bcm5785_lpc_read_resources(device_t dev) +static void bcm5785_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -70,7 +70,7 @@ static void bcm5785_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void bcm5785_lpc_enable_childrens_resources(device_t dev) +static void bcm5785_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; uint32_t reg; @@ -78,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config8(dev, 0x44);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -114,13 +114,13 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
}
-static void bcm5785_lpc_enable_resources(device_t dev) +static void bcm5785_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); bcm5785_lpc_enable_childrens_resources(dev); }
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 62eab45..d2b908e 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -73,7 +73,7 @@ static void sata_init(struct device *dev) } }
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 3745cef..0e42863 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -33,7 +33,7 @@
#define NMI_OFF 0
-static void sb_init(device_t dev) +static void sb_init(struct device * dev) { uint8_t byte; uint8_t byte_old; @@ -56,7 +56,7 @@ static void sb_init(device_t dev)
}
-static void bcm5785_sb_read_resources(device_t dev) +static void bcm5785_sb_read_resources(struct device * dev) { struct resource *res;
@@ -76,7 +76,7 @@ static void bcm5785_sb_read_resources(device_t dev)
}
-static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -90,7 +90,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); }
-static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(struct device * dev, uint8_t val) { unsigned device; struct resource *res; @@ -104,7 +104,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val) return do_smbus_send_byte(res->base, device, val); }
-static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(struct device * dev, uint8_t address) { unsigned device; struct resource *res; @@ -118,7 +118,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) return do_smbus_read_byte(res->base, device, address); }
-static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(struct device * dev, uint8_t address, uint8_t val) { unsigned device; struct resource *res; @@ -139,7 +139,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, };
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index cb4a498..b9c2452 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -37,7 +37,7 @@ static void usb_init(struct device *dev)
}
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d4f263b..b65fd11 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -95,7 +95,7 @@ static const unsigned char irq_to_int_routing[16] = { /* keyboard controller system flag timeout : 400 ms */ #define KBC_TIMEOUT_SYS_FLAG 400
-static u8 get_pci_dev_func(device_t dev) +static u8 get_pci_dev_func(struct device * dev) { return PCI_FUNC(dev->path.pci.devfn); } @@ -182,7 +182,7 @@ static void pci_routing_fixup(struct device *dev) /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */ for (i = 0; i < slot_num; i++) { unsigned int funct; - device_t pdev; + struct device * pdev; u8 irq;
/* Each slot may contain up to eight functions. */ @@ -515,7 +515,7 @@ static void fix_cmos_rtc_time(void) } }
-static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) +static void vortex86_sb_set_io_resv(struct device * dev, unsigned index, u32 base, u32 size) { struct resource *res; res = new_resource(dev, index); @@ -525,7 +525,7 @@ static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(struct device * dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; @@ -536,7 +536,7 @@ static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 fla res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; }
-static void vortex86_sb_read_resources(device_t dev) +static void vortex86_sb_read_resources(struct device * dev) { u32 flash_size = 8 * 1024 * 1024;
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0e3a4f6..04f38d1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -101,9 +101,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */
-static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info;
@@ -143,7 +143,7 @@ static void pch_pirq_init(device_t dev) } }
-static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -172,7 +172,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); }
-static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -393,7 +393,7 @@ static void enable_hpet(void) RCBA32(HPTC) = reg32; }
-static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { u32 reg32; u16 reg16; @@ -581,7 +581,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); }
-static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -645,13 +645,13 @@ static void pch_lpc_read_resources(device_t dev) } }
-static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); }
-static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -660,7 +660,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); }
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 44c7273..a316ea0 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -120,7 +120,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) }
#ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -548,7 +548,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */
/* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -615,7 +615,7 @@ static me_bios_path intel_me_path(device_t dev) }
/* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -645,7 +645,7 @@ static int intel_mei_setup(device_t dev) }
/* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -692,14 +692,14 @@ static int intel_me_extend_valid(device_t dev) }
/* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); }
/* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev);
@@ -741,7 +741,7 @@ static void intel_me_init(device_t dev) } }
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index cb5699e..897470b 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -211,7 +211,7 @@ static void sata_init(struct device *dev) pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); }
-static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -236,7 +236,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); }
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 2ea9a24..e5783e7 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -322,7 +322,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev; + struct device * dev; ich9_spi_regs *ich9_spi; uint16_t hsfs;
diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c index b5b77ef..b2dcd06 100644 --- a/src/southbridge/intel/esb6300/lpc.c +++ b/src/southbridge/intel/esb6300/lpc.c @@ -24,7 +24,7 @@ #endif
#define SERIRQ_CNTL 0x64 -static void esb6300_enable_serial_irqs(device_t dev) +static void esb6300_enable_serial_irqs(struct device *dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -32,14 +32,14 @@ static void esb6300_enable_serial_irqs(device_t dev) }
#define PCI_DMA_CFG 0x90 -static void esb6300_pci_dma_cfg(device_t dev) +static void esb6300_pci_dma_cfg(struct device *dev) { /* Set PCI DMA CFG to lpc I/F DMA */ pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); }
#define LPC_EN 0xe6 -static void esb6300_enable_lpc(device_t dev) +static void esb6300_enable_lpc(struct device *dev) { /* lpc i/f enable */ pci_write_config8(dev, LPC_EN, 0x0d); @@ -48,7 +48,7 @@ static void esb6300_enable_lpc(device_t dev) typedef struct southbridge_intel_esb6300_config config_t;
static void set_esb6300_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_use_sel, gpio_use_sel2;
@@ -81,7 +81,7 @@ static void set_esb6300_gpio_use_sel( }
static void set_esb6300_gpio_direction( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_io_sel, gpio_io_sel2;
@@ -114,7 +114,7 @@ static void set_esb6300_gpio_direction( }
static void set_esb6300_gpio_level( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_lvl, gpio_lvl2; uint32_t gpio_blink; @@ -154,7 +154,7 @@ static void set_esb6300_gpio_level( }
static void set_esb6300_gpio_inv( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_inv;
@@ -176,7 +176,7 @@ static void set_esb6300_gpio_inv( outl(gpio_inv, res->base + 0x2c); }
-static void esb6300_pirq_init(device_t dev) +static void esb6300_pirq_init(struct device *dev) { config_t *config;
@@ -192,7 +192,7 @@ static void esb6300_pirq_init(device_t dev) }
-static void esb6300_gpio_init(device_t dev) +static void esb6300_gpio_init(struct device *dev) { struct resource *res; config_t *config; @@ -303,7 +303,7 @@ static void lpc_init(struct device *dev) isa_dma_init(); }
-static void esb6300_lpc_read_resources(device_t dev) +static void esb6300_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -335,7 +335,7 @@ static void esb6300_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void esb6300_lpc_enable_resources(device_t dev) +static void esb6300_lpc_enable_resources(struct device *dev) { uint8_t acpi_cntl, gpio_cntl;
diff --git a/src/southbridge/intel/esb6300/sata.c b/src/southbridge/intel/esb6300/sata.c index b08f0ed..cc11006 100644 --- a/src/southbridge/intel/esb6300/sata.c +++ b/src/southbridge/intel/esb6300/sata.c @@ -42,7 +42,7 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA Enabled\n"); }
-static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void esb6300_sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* This value is also visible in usb1, usb2 and smbus functions */ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index e5d63b6..edd5dc7 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -116,9 +116,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */
-static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info;
@@ -158,7 +158,7 @@ static void pch_pirq_init(device_t dev) } }
-static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -187,7 +187,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); }
-static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -547,7 +547,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); }
-static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -608,18 +608,18 @@ static void pch_lpc_read_resources(device_t dev) } }
-static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); }
-static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { pch_enable(dev); }
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index 2282378..ddec118 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -119,7 +119,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) }
#ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -547,7 +547,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */
/* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -614,7 +614,7 @@ static me_bios_path intel_me_path(device_t dev) }
/* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -644,7 +644,7 @@ static int intel_mei_setup(device_t dev) }
/* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -691,14 +691,14 @@ static int intel_me_extend_valid(device_t dev) }
/* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); }
/* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev);
@@ -740,7 +740,7 @@ static void intel_me_init(device_t dev) } }
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c index 591bdbc..cbbb76b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/sata.c +++ b/src/southbridge/intel/fsp_bd82x6x/sata.c @@ -82,11 +82,11 @@ static void sata_init(struct device *dev)
}
-static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { }
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 8576b61..9b1df7a 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -113,8 +113,8 @@ static void soc_enable_serial_irqs(struct device *dev) */ static void write_pci_config_irqs(void) { - device_t irq_dev; - device_t targ_dev; + struct device *irq_dev; + struct device *targ_dev; uint8_t int_line = 0; uint8_t original_int_pin = 0; uint8_t new_int_pin = 0; @@ -197,7 +197,7 @@ static void write_pci_config_irqs(void) printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); }
-static void soc_pirq_init(device_t dev) +static void soc_pirq_init(struct device *dev) { int i, j; int pirq; @@ -242,7 +242,7 @@ static void soc_pirq_init(device_t dev) write_pci_config_irqs(); }
-static void soc_power_options(device_t dev) +static void soc_power_options(struct device *dev) { u8 reg8; u16 pmbase; @@ -344,7 +344,7 @@ static void lpc_init(struct device *dev) soc_disable_smm_only_flashing(dev); }
-static void soc_lpc_read_resources(device_t dev) +static void soc_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -405,17 +405,17 @@ static void soc_lpc_read_resources(device_t dev) } }
-static void soc_lpc_enable_resources(device_t dev) +static void soc_lpc_enable_resources(struct device *dev) { return pci_dev_enable_resources(dev); }
-static void soc_lpc_enable(device_t dev) +static void soc_lpc_enable(struct device *dev) { soc_enable(dev); }
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index f672e4c..dcaa230 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -95,11 +95,11 @@ static void sata_init(struct device *dev)
}
-static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { }
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 6df99fd..c4e8a1c 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -370,7 +370,7 @@ void spi_init(void) { int ich_version = 0; uint8_t bios_cntl; - device_t dev; + struct device * dev; uint32_t ids; uint16_t vendor_id, device_id;
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index ba74f30..6cfec63 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif
-static void i3100_enable_serial_irqs(device_t dev) +static void i3100_enable_serial_irqs(struct device *dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -62,7 +62,7 @@ static void i3100_enable_serial_irqs(device_t dev) typedef struct southbridge_intel_i3100_config config_t;
static void set_i3100_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_use_sel, gpio_use_sel2; int i; @@ -95,7 +95,7 @@ static void set_i3100_gpio_use_sel( }
static void set_i3100_gpio_direction( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_io_sel, gpio_io_sel2; int i; @@ -128,7 +128,7 @@ static void set_i3100_gpio_direction( }
static void set_i3100_gpio_level( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_lvl, gpio_lvl2; u32 gpio_blink; @@ -172,7 +172,7 @@ static void set_i3100_gpio_level( }
static void set_i3100_gpio_inv( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { u32 gpio_inv; int i; @@ -196,9 +196,9 @@ static void set_i3100_gpio_inv( outl(gpio_inv, res->base + 0x2c); }
-static void i3100_pirq_init(device_t dev) +static void i3100_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; config_t *config;
/* Get the chip configuration */ @@ -245,7 +245,7 @@ static void i3100_pirq_init(device_t dev)
}
-static void i3100_power_options(device_t dev) { +static void i3100_power_options(struct device *dev) { u8 reg8; u16 reg16; int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; @@ -308,7 +308,7 @@ static void i3100_power_options(device_t dev) { // i82801gx_gpi_routing(dev); }
-static void i3100_gpio_init(device_t dev) +static void i3100_gpio_init(struct device *dev) { struct resource *res; config_t *config; @@ -384,7 +384,7 @@ static void lpc_init(struct device *dev) i8259_configure_irq_trigger(9, 1); }
-static void i3100_lpc_read_resources(device_t dev) +static void i3100_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -424,7 +424,7 @@ static void i3100_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM; }
-static void i3100_lpc_enable_resources(device_t dev) +static void i3100_lpc_enable_resources(struct device *dev) { u8 acpi_cntl, gpio_cntl;
diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c index 0740440..6f4ebf9 100644 --- a/src/southbridge/intel/i3100/sata.c +++ b/src/southbridge/intel/i3100/sata.c @@ -111,7 +111,7 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA Enabled\n"); }
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index 11519c1..c96ac00 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -122,7 +122,7 @@ static void i82801ax_enable_serial_irqs(struct device *dev) /* TODO: Explain/#define the real meaning of these magic numbers. */ }
-static void i82801ax_pirq_init(device_t dev) +static void i82801ax_pirq_init(struct device *dev) { u8 reg8; config_t *config = dev->chip_info; @@ -140,7 +140,7 @@ static void i82801ax_pirq_init(device_t dev) pci_write_config8(dev, PIRQD_ROUT, reg8); }
-static void i82801ax_power_options(device_t dev) +static void i82801ax_power_options(struct device *dev) { uint8_t byte; int pwr_on = -1; @@ -170,7 +170,7 @@ static void i82801ax_power_options(device_t dev) } }
-static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); pci_write_config8(dev, GPIO_CNTL, GPIO_EN); @@ -211,7 +211,7 @@ static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); }
-static void i82801ax_lpc_decode_en(device_t dev) +static void i82801ax_lpc_decode_en(struct device *dev) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -255,7 +255,7 @@ static void lpc_init(struct device *dev) i82801ax_lpc_decode_en(dev); }
-static void i82801ax_lpc_read_resources(device_t dev) +static void i82801ax_lpc_read_resources(struct device *dev) { struct resource *res;
diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 278d65c..3bd6570 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -123,7 +123,7 @@ static void i82801bx_enable_serial_irqs(struct device *dev) /* TODO: Explain/#define the real meaning of these magic numbers. */ }
-static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) +static void i82801bx_pirq_init(struct device *dev, uint16_t ich_model) { u8 reg8; config_t *config = dev->chip_info; @@ -154,7 +154,7 @@ static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) pci_write_config8(dev, PIRQH_ROUT, reg8); }
-static void i82801bx_power_options(device_t dev) +static void i82801bx_power_options(struct device *dev) { uint8_t byte; int pwr_on = -1; @@ -184,7 +184,7 @@ static void i82801bx_power_options(device_t dev) } }
-static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); @@ -226,7 +226,7 @@ static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); }
-static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model) +static void i82801bx_lpc_decode_en(struct device *dev, uint16_t ich_model) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -273,7 +273,7 @@ static void lpc_init(struct device *dev) i82801bx_lpc_decode_en(dev, ich_model); }
-static void i82801bx_lpc_read_resources(device_t dev) +static void i82801bx_lpc_read_resources(struct device *dev) { struct resource *res;
diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index f6c33b7..9978842 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -199,7 +199,7 @@ static void lpc_init(struct device *dev) i82801cx_1f0_misc(dev); }
-static void i82801cx_lpc_read_resources(device_t dev) +static void i82801cx_lpc_read_resources(struct device *dev) { struct resource *res;
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 1b23fad..c5821c6 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -85,7 +85,7 @@ static void i82801dx_enable_serial_irqs(struct device *dev) (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); }
-static void i82801dx_pirq_init(device_t dev) +static void i82801dx_pirq_init(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -100,7 +100,7 @@ static void i82801dx_pirq_init(device_t dev) pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); }
-static void i82801dx_power_options(device_t dev) +static void i82801dx_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -179,7 +179,7 @@ static void i82801dx_power_options(device_t dev) outl(reg32, pmbase + 0x04); }
-static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { /* This should be done in romstage.c already */ pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); @@ -221,7 +221,7 @@ static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); }
-static void i82801dx_lpc_decode_en(device_t dev) +static void i82801dx_lpc_decode_en(struct device *dev) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -305,7 +305,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); }
-static void i82801dx_lpc_read_resources(device_t dev) +static void i82801dx_lpc_read_resources(struct device *dev) { struct resource *res;
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 1823e65..7703d14 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -61,7 +61,7 @@ static void i82801ex_general_cntl(struct device *dev) }
#define SERIRQ_CNTL 0x64 -static void i82801ex_enable_serial_irqs(device_t dev) +static void i82801ex_enable_serial_irqs(struct device *dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -69,14 +69,14 @@ static void i82801ex_enable_serial_irqs(device_t dev) }
#define PCI_DMA_CFG 0x90 -static void i82801ex_pci_dma_cfg(device_t dev) +static void i82801ex_pci_dma_cfg(struct device *dev) { /* Set PCI DMA CFG to lpc I/F DMA */ pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); }
#define LPC_EN 0xe6 -static void i82801ex_enable_lpc(device_t dev) +static void i82801ex_enable_lpc(struct device *dev) { /* lpc i/f enable */ pci_write_config8(dev, LPC_EN, 0x0d); @@ -85,7 +85,7 @@ static void i82801ex_enable_lpc(device_t dev) typedef struct southbridge_intel_i82801ex_config config_t;
static void set_i82801ex_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_use_sel, gpio_use_sel2; int i; @@ -114,7 +114,7 @@ static void set_i82801ex_gpio_use_sel( }
static void set_i82801ex_gpio_direction( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_io_sel, gpio_io_sel2; int i; @@ -143,7 +143,7 @@ static void set_i82801ex_gpio_direction( }
static void set_i82801ex_gpio_level( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_lvl, gpio_lvl2; uint32_t gpio_blink; @@ -178,7 +178,7 @@ static void set_i82801ex_gpio_level( }
static void set_i82801ex_gpio_inv( - device_t dev, struct resource *res, config_t *config) + struct device *dev, struct resource *res, config_t *config) { uint32_t gpio_inv; int i; @@ -198,7 +198,7 @@ static void set_i82801ex_gpio_inv( outl(gpio_inv, res->base + 0x2c); }
-static void i82801ex_pirq_init(device_t dev) +static void i82801ex_pirq_init(struct device *dev) { config_t *config;
@@ -214,7 +214,7 @@ static void i82801ex_pirq_init(device_t dev) }
-static void i82801ex_gpio_init(device_t dev) +static void i82801ex_gpio_init(struct device *dev) { struct resource *res; config_t *config; @@ -319,7 +319,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); }
-static void i82801ex_lpc_read_resources(device_t dev) +static void i82801ex_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -351,7 +351,7 @@ static void i82801ex_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void i82801ex_lpc_enable_resources(device_t dev) +static void i82801ex_lpc_enable_resources(struct device *dev) { /* Enable the normal PCI resources. */ pci_dev_enable_resources(dev); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 3b6b71a..021884d 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -90,9 +90,9 @@ static void i82801gx_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */
-static void i82801gx_pirq_init(device_t dev) +static void i82801gx_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info;
@@ -132,7 +132,7 @@ static void i82801gx_pirq_init(device_t dev) } }
-static void i82801gx_gpi_routing(device_t dev) +static void i82801gx_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -161,7 +161,7 @@ static void i82801gx_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); }
-static void i82801gx_power_options(device_t dev) +static void i82801gx_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -265,7 +265,7 @@ static void i82801gx_power_options(device_t dev) outl(reg32, pmbase + 0x04); }
-static void i82801gx_configure_cstates(device_t dev) +static void i82801gx_configure_cstates(struct device *dev) { u8 reg8;
@@ -457,7 +457,7 @@ static void lpc_init(struct device *dev)
void acpi_fill_fadt(acpi_fadt_t * fadt) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
@@ -575,7 +575,7 @@ void acpi_fill_fadt(acpi_fadt_t * fadt) } }
-static void i82801gx_lpc_read_resources(device_t dev) +static void i82801gx_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -601,7 +601,7 @@ static void i82801gx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index ea29986..e0794d6 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -188,7 +188,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x94, reg32); }
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 664088c..b4ded0f 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -92,9 +92,9 @@ static void i82801ix_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */
-static void i82801ix_pirq_init(device_t dev) +static void i82801ix_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info;
@@ -134,7 +134,7 @@ static void i82801ix_pirq_init(device_t dev) } }
-static void i82801ix_gpi_routing(device_t dev) +static void i82801ix_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -163,7 +163,7 @@ static void i82801ix_gpi_routing(device_t dev) pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); }
-static void i82801ix_power_options(device_t dev) +static void i82801ix_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -295,7 +295,7 @@ static void i82801ix_power_options(device_t dev) outl(reg32, pmbase + 0x10); }
-static void i82801ix_configure_cstates(device_t dev) +static void i82801ix_configure_cstates(struct device *dev) { u8 reg8;
@@ -471,7 +471,7 @@ static void lpc_init(struct device *dev) #endif }
-static void i82801ix_lpc_read_resources(device_t dev) +static void i82801ix_lpc_read_resources(struct device *dev) { /* * I/O Resources @@ -527,7 +527,7 @@ static void i82801ix_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 10c8a2b..0fcf7bd 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -141,7 +141,7 @@ static void sata_program_indexed(struct device *const dev, const int is_mobile) pci_write_config32(dev, D31F2_SDAT, reg32); }
-static void sata_init(struct device *const dev) +static void sata_init(struct device *dev) { u16 reg16;
@@ -212,7 +212,7 @@ static void sata_init(struct device *const dev) pci_write_config32(dev, 0x94, sclkcg);
if (is_mobile && config->sata_traffic_monitor) { - const device_t lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + const struct device *lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) >> 3) & 3) == 3) { u8 reg8 = pci_read_config8(dev, 0x9c); @@ -228,7 +228,7 @@ static void sata_init(struct device *const dev) sata_program_indexed(dev, is_mobile); }
-static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ const config_t *const config = dev->chip_info; @@ -255,7 +255,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); }
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index a833a3d..31b8389 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -101,9 +101,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */
-static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info;
@@ -143,7 +143,7 @@ static void pch_pirq_init(device_t dev) } }
-static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -172,7 +172,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); }
-static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -400,7 +400,7 @@ static void enable_hpet(void) write32(0xfed00010, read32(0xfed00010) | 1); }
-static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { u32 reg32; u16 reg16; @@ -578,7 +578,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); }
-static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -639,13 +639,13 @@ static void pch_lpc_read_resources(device_t dev) } }
-static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); }
-static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -654,7 +654,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); }
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 99920f5..0a5b20f 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -120,7 +120,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) }
#ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -430,7 +430,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */
/* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -497,7 +497,7 @@ static me_bios_path intel_me_path(device_t dev) }
/* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -527,7 +527,7 @@ static int intel_mei_setup(device_t dev) }
/* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -574,14 +574,14 @@ static int intel_me_extend_valid(device_t dev) }
/* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); }
/* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev);
@@ -616,7 +616,7 @@ static void intel_me_init(device_t dev) } }
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 5f3c4d3..cee66c5 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -212,7 +212,7 @@ static void sata_init(struct device *dev) pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); }
-static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -237,7 +237,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); }
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a202424..6adc8a5 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -107,9 +107,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */
-static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info;
@@ -149,7 +149,7 @@ static void pch_pirq_init(device_t dev) } }
-static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -178,7 +178,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); }
-static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16; @@ -416,7 +416,7 @@ static void enable_hpet(void) reg32 = RCBA32(HPTC); }
-static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { /* LynxPoint Mobile */ u32 reg32; @@ -441,7 +441,7 @@ static void enable_clock_gating(device_t dev) RCBA32_OR(0x38c0, 0x7); // SPI Dynamic }
-static void enable_lp_clock_gating(device_t dev) +static void enable_lp_clock_gating(struct device *dev) { /* LynxPoint LP */ u32 reg32; @@ -591,7 +591,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); }
-static void pch_lpc_add_mmio_resources(device_t dev) +static void pch_lpc_add_mmio_resources(struct device *dev) { u32 reg; struct resource *res; @@ -653,7 +653,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res;
@@ -666,7 +666,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -679,7 +679,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) } }
-static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -704,7 +704,7 @@ static void pch_lpc_add_io_resources(device_t dev) pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); }
-static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { global_nvs_t *gnvs;
@@ -723,7 +723,7 @@ static void pch_lpc_read_resources(device_t dev) memset(gnvs, 0, sizeof(global_nvs_t)); }
-static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -732,7 +732,7 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); }
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 43a99c8..0812fe5 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -305,7 +305,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x300, reg32); }
-static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -326,7 +326,7 @@ static void sata_enable(device_t dev) pci_write_config16(dev, 0x90, map); }
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index 7d209b1..beaf090 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -76,9 +76,9 @@ typedef struct southbridge_intel_sch_config config_t; #define PIRQG 0x0B #define PIRQH 0x0C
-static void sch_pirq_init(device_t dev) +static void sch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev;
/* Get the chip configuration */ config_t *config = dev->chip_info; @@ -151,7 +151,7 @@ static void lpc_init(struct device *dev) sch_fixups(dev); }
-static void sch_lpc_read_resources(device_t dev) +static void sch_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -177,7 +177,7 @@ static void sch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 353a4bd..a285938 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -28,9 +28,9 @@
static u32 final_reg;
-static device_t find_lpc_dev(device_t dev, unsigned devfn) +static struct device * find_lpc_dev(struct device * dev, unsigned devfn) { - device_t lpc_dev; + struct device * lpc_dev;
lpc_dev = dev_find_slot(dev->bus->secondary, devfn); if (!lpc_dev) @@ -57,9 +57,9 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn) return lpc_dev; }
-void ck804_enable(device_t dev) +void ck804_enable(struct device * dev) { - device_t lpc_dev; + struct device * lpc_dev; unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; u32 reg_old, reg; u8 byte; @@ -188,7 +188,7 @@ void ck804_enable(device_t dev) } }
-static void ck804_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void ck804_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 9b6049c..d62075f 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif
-static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device *dev) { u32 dword; struct resource *res; @@ -69,12 +69,12 @@ static void lpc_common_init(device_t dev) #endif }
-static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device *dev) { lpc_common_init(dev); }
-static void rom_dummy_write(device_t dev) +static void rom_dummy_write(struct device *dev) { u8 old, new; u8 *p; @@ -104,7 +104,7 @@ static void rom_dummy_write(device_t dev)
unsigned pm_base = 0;
-static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte, byte_old; int on, nmi_option; @@ -170,7 +170,7 @@ static void lpc_init(device_t dev) rom_dummy_write(dev); }
-static void ck804_lpc_read_resources(device_t dev) +static void ck804_lpc_read_resources(struct device *dev) { struct resource *res; unsigned long index; @@ -215,7 +215,7 @@ static void ck804_lpc_read_resources(device_t dev) } }
-static void ck804_lpc_set_resources(device_t dev) +static void ck804_lpc_set_resources(struct device *dev) { u8 byte; struct resource *res; @@ -251,7 +251,7 @@ static void ck804_lpc_set_resources(device_t dev) * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. */ -static void ck804_lpc_enable_childrens_resources(device_t dev) +static void ck804_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_var[4]; @@ -260,7 +260,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -307,7 +307,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); }
-static void ck804_lpc_enable_resources(device_t dev) +static void ck804_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); ck804_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index dd6a5f4..62967bf 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -28,7 +28,7 @@ #include "ck804.h" #include "smbus.h"
-static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -42,7 +42,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); }
-static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -56,7 +56,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); }
-static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -70,7 +70,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); }
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 67433d3..954e305 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -254,7 +254,7 @@ static void azalia_init(struct device *dev) } }
-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void azalia_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 92f9d03..865c023 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -24,7 +24,7 @@
static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
/* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 11c2c4f..a2a3b22 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -57,7 +57,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif
-static void lpc_common_init(device_t dev, int master) +static void lpc_common_init(struct device *dev, int master) { u8 byte; u32 ioapic_base; @@ -74,7 +74,7 @@ static void lpc_common_init(device_t dev, int master) clear_ioapic(ioapic_base); }
-static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device *dev) { lpc_common_init(dev, 0); } @@ -88,7 +88,7 @@ static void enable_hpet(struct device *dev) printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); }
-static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { u8 byte, byte_old; int on, nmi_option; @@ -161,7 +161,7 @@ static void lpc_init(device_t dev) enable_hpet(dev); }
-static void mcp55_lpc_read_resources(device_t dev) +static void mcp55_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -193,7 +193,7 @@ static void mcp55_lpc_read_resources(device_t dev) * * @param dev The device whose children's resources are to be enabled. */ -static void mcp55_lpc_enable_childrens_resources(device_t dev) +static void mcp55_lpc_enable_childrens_resources(struct device *dev) { u32 reg, reg_var[4]; int i, var_num = 0; @@ -202,7 +202,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -250,7 +250,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); }
-static void mcp55_lpc_enable_resources(device_t dev) +static void mcp55_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); mcp55_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 4fb3391..20b33b4 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -30,7 +30,7 @@
#ifndef __PRE_RAM__ #include "chip.h" -void mcp55_enable(device_t dev); +void mcp55_enable(struct device * dev); extern struct pci_operations mcp55_pci_ops; #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 3e0b87e..e28a896 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -31,7 +31,7 @@ #include "mcp55.h" #include "smbus.h"
-static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -45,7 +45,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); }
-static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -59,7 +59,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); }
-static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -73,7 +73,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); }
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; @@ -97,7 +97,7 @@ static struct smbus_bus_operations lops_smbus_bus = { unsigned pm_base; #endif
-static void mcp55_sm_read_resources(device_t dev) +static void mcp55_sm_read_resources(struct device * dev) { unsigned long index;
@@ -110,7 +110,7 @@ static void mcp55_sm_read_resources(device_t dev) compact_resources(dev); }
-static void mcp55_sm_init(device_t dev) +static void mcp55_sm_init(struct device * dev) { #if CONFIG_HAVE_ACPI_TABLES struct resource *res; diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index 3695023..4b3a228 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -23,7 +23,7 @@
static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
/* Find the device. */ dev = pci_locate_device_on_bus( diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 0e11c6f..55a5e43 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -56,7 +56,7 @@
#undef SLAVE_INIT
-static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device *dev) { uint8_t byte; uint32_t ioapic_base; @@ -71,13 +71,13 @@ static void lpc_common_init(device_t dev) }
#ifdef SLAVE_INIT -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device *dev) { lpc_common_init(dev); } #endif
-static void lpc_usb_legacy_init(device_t dev) +static void lpc_usb_legacy_init(struct device *dev) { uint16_t acpi_base;
@@ -87,7 +87,7 @@ static void lpc_usb_legacy_init(device_t dev) outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba); }
-static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { uint8_t byte; uint8_t byte_old; @@ -156,7 +156,7 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "LPC_INIT <--------\n"); }
-static void sis966_lpc_read_resources(device_t dev) +static void sis966_lpc_read_resources(struct device *dev) { struct resource *res;
@@ -187,7 +187,7 @@ static void sis966_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void sis966_lpc_enable_childrens_resources(device_t dev) +static void sis966_lpc_enable_childrens_resources(struct device *dev) { struct bus *link; uint32_t reg, reg_var[4]; @@ -197,7 +197,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0);
for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -238,13 +238,13 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
}
-static void sis966_lpc_enable_resources(device_t dev) +static void sis966_lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); sis966_lpc_enable_childrens_resources(dev); }
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c index 3f8c28f..1f942aa 100644 --- a/src/southbridge/sis/sis966/sata.c +++ b/src/southbridge/sis/sis966/sata.c @@ -171,7 +171,7 @@ for (i=0;i<10;i++){
}
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/via/vt8231/early_serial.c b/src/southbridge/via/vt8231/early_serial.c index a0aec65..8c500b9 100644 --- a/src/southbridge/via/vt8231/early_serial.c +++ b/src/southbridge/via/vt8231/early_serial.c @@ -33,7 +33,7 @@ static void vt8231_writesioword(uint16_t reg, uint16_t val) static void enable_vt8231_serial(void) { uint8_t c; - device_t dev; + pnp_devfn_t dev; post_code(0x06); dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
diff --git a/src/southbridge/via/vt8231/lpc.c b/src/southbridge/via/vt8231/lpc.c index c6b74fd..862b1ad 100644 --- a/src/southbridge/via/vt8231/lpc.c +++ b/src/southbridge/via/vt8231/lpc.c @@ -124,7 +124,7 @@ static void vt8231_init(struct device *dev) cmos_init(0); }
-static void vt8231_read_resources(device_t dev) +static void vt8231_read_resources(struct device *dev) { struct resource *res;
diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c index 2c78481..396b647 100644 --- a/src/southbridge/via/vt8235/lpc.c +++ b/src/southbridge/via/vt8235/lpc.c @@ -104,7 +104,7 @@ static void pci_routing_fixup(struct device *dev) * can't figure out how to do !!!! */
-static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { // Set gen config 0 pci_write_config8(dev, 0x80, 0x20); @@ -214,7 +214,7 @@ static void vt8235_init(struct device *dev)
/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this device has a resource to set - so set a dummy one */ -static void vt8235_read_resources(device_t dev) +static void vt8235_read_resources(struct device *dev) { struct resource *res;
@@ -232,7 +232,7 @@ static void vt8235_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void vt8235_set_resources(device_t dev) +static void vt8235_set_resources(struct device *dev) { //struct resource *resource; //resource = find_resource(dev,1); diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 9e8f6f6..70b6120 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -66,7 +66,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin) static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT - device_t pdev; + struct device *pdev; #endif
/* PCI PNP Interrupt Routing INTE/F - disable */ @@ -148,7 +148,7 @@ static void pci_routing_fixup(struct device *dev) * This avoids having to handle any System Management Interrupts (SMIs). */
-static void setup_pm(device_t dev) +static void setup_pm(struct device *dev) { u16 tmp; struct southbridge_via_vt8237r_config *cfg; @@ -568,7 +568,7 @@ static void vt8237_common_init(struct device *dev) cmos_init(0); }
-static void vt8237r_read_resources(device_t dev) +static void vt8237r_read_resources(struct device *dev) { struct resource *res;
@@ -640,7 +640,7 @@ static void southbridge_init_common(struct device *dev) }
-static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void vt8237_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config16(dev, 0x70, vendor); pci_write_config16(dev, 0x72, device); diff --git a/src/southbridge/via/vt8237r/sata.c b/src/southbridge/via/vt8237r/sata.c index 606c33e..0246d54 100644 --- a/src/southbridge/via/vt8237r/sata.c +++ b/src/southbridge/via/vt8237r/sata.c @@ -96,7 +96,7 @@ static void sata_ii_init(struct device *dev) }
-static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void vt8237_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config16(dev, 0xd4, vendor); pci_write_config16(dev, 0xd6, device); diff --git a/src/southbridge/via/vt82c686/early_serial.c b/src/southbridge/via/vt82c686/early_serial.c index 55742a7..9cdf943 100644 --- a/src/southbridge/via/vt82c686/early_serial.c +++ b/src/southbridge/via/vt82c686/early_serial.c @@ -48,10 +48,10 @@ static void vt82c686_sio_write(uint8_t index, uint8_t value) * @param dev TODO * @param iobase TODO */ -static void vt82c686_enable_serial(device_t dev, unsigned iobase) +static void vt82c686_enable_serial(pnp_devfn_t dev, unsigned iobase) { uint8_t reg; - device_t sbdev; + pnp_devfn_t sbdev;
/* TODO: Use info from 'dev' and 'iobase'. */ /* TODO: Only enable one serial port (depending on config) or both? */
-
Edward O'Callaghan