[L] Change in coreboot[main]: soc/intel/pantherlake: Add FSP-S programming

[Jérémy Compostella (Code Review)]

Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N, Ronak Kanabar, Subrata Banik.

Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84552?usp=email )

Change subject: soc/intel/pantherlake: Add FSP-S programming
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Patch Set 14:

(1 comment)

File src/soc/intel/pantherlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/84552/comment/f73cc184_6228a0d8?usp... :
PS11, Line 301: 	max_port = get_max_tcss_port();
              : 	for (i = 0; i < max_port; i++)
> > It would definitely save few CPU cycles. […]

There was no way I would introduce inconsistent code as I would have if I had followed your proposal so I created [84616: soc/intel/pantherlake: Remove soc_info.[hc] interface](https://review.coreboot.org/c/coreboot/+/84616) instead. Obviously, the CPU cycles saving is completely ridiculous and not my concern here. However, I agree that these functions were not adding any values and more importantly, this was the final selling point for me, it was preventing the compiler from detecting arrays overflow.