Change in coreboot[master]: soc/intel/cache_as_ram.S: Fix CAR issues with Bootguard - coreboot-gerrit

24 Jun 2021


      Attention is currently required from: Michał Żygowski, Angel Pons, Patrick Rudolph.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55791 )
Change subject: soc/intel/cache_as_ram.S: Fix CAR issues with Bootguard
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Patch Set 3:
(2 comments)
Patchset:
PS2:
...
So now it should be possible to setup CAR without FSP-T right?
Yes!
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/55791/comment/ea83f3c6_c18cc3fc 
PS2, Line 215: sfenche
...
typo: `sfence`
Done
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id5d77295f6d24f9d2bc23f39f8772fd172ac8910
Gerrit-Change-Number: 55791
Gerrit-PatchSet: 3
Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz
Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
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