Patch set updated for coreboot: [intel/apollolake]: Add support to enable google ChromeEC
Shaunak Saha (shaunak.saha@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14967
-gerrit
commit 5a8c7a397fc23b705494ecb8afe7ef570833e859 Author: Shaunak Saha shaunak.saha@intel.com Date: Wed May 25 11:34:43 2016 -0700
[intel/apollolake]: Add support to enable google ChromeEC
ChromeEC is needed for EC controlled features to work properly. This patch adds neccessary support in soc/intel so that mainboard asl files can include the ChromeEC e.g. PNOT method and LPCB and also the nvs fields.
BUG = 53096 TEST = This patch is needed by the mainboard specific ASL change to include src/ec/google/chromeec/acpi/ec.asl
Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9 Signed-off-by: Shaunak Saha shaunak.saha@intel.com --- src/soc/intel/apollolake/acpi/cpu.asl | 118 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/globalnvs.asl | 7 +- src/soc/intel/apollolake/acpi/lpc.asl | 23 +++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 + src/soc/intel/apollolake/include/soc/nvs.h | 7 +- 5 files changed, 156 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/apollolake/acpi/cpu.asl b/src/soc/intel/apollolake/acpi/cpu.asl new file mode 100644 index 0000000..a202ceb --- /dev/null +++ b/src/soc/intel/apollolake/acpi/cpu.asl @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* These devices are created at runtime */ +External (_PR.CP00, DeviceObj) +External (_PR.CP01, DeviceObj) +External (_PR.CP02, DeviceObj) +External (_PR.CP03, DeviceObj) +External (_PR.CP04, DeviceObj) +External (_PR.CP05, DeviceObj) +External (_PR.CP06, DeviceObj) +External (_PR.CP07, DeviceObj) + +/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ +Method (PNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (_PR.CP00, 0x81) // _CST + Notify (_PR.CP01, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (_PR.CP02, 0x81) // _CST + Notify (_PR.CP03, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (_PR.CP04, 0x81) // _CST + Notify (_PR.CP05, 0x81) // _CST + Notify (_PR.CP06, 0x81) // _CST + Notify (_PR.CP07, 0x81) // _CST + } +} + +/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ +Method (PPCN) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (_PR.CP00, 0x80) // _PPC + Notify (_PR.CP01, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (_PR.CP02, 0x80) // _PPC + Notify (_PR.CP03, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (_PR.CP04, 0x80) // _PPC + Notify (_PR.CP05, 0x80) // _PPC + Notify (_PR.CP06, 0x80) // _PPC + Notify (_PR.CP07, 0x80) // _PPC + } +} + +/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ +Method (TNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (_PR.CP00, 0x82) // _TPC + Notify (_PR.CP01, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (_PR.CP02, 0x82) // _TPC + Notify (_PR.CP03, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (_PR.CP04, 0x82) // _TPC + Notify (_PR.CP05, 0x82) // _TPC + Notify (_PR.CP06, 0x82) // _TPC + Notify (_PR.CP07, 0x82) // _TPC + } +} + +/* Return a package containing enabled processor entries */ +Method (PPKG) +{ + If (LGreaterEqual (\PCNT, 8)) { + Return (Package() + { + _PR.CP00, + _PR.CP01, + _PR.CP02, + _PR.CP03, + _PR.CP04, + _PR.CP05, + _PR.CP06, + _PR.CP07 + }) + } ElseIf (LGreaterEqual (\PCNT, 4)) { + Return (Package () + { + _PR.CP00, + _PR.CP01, + _PR.CP02, + _PR.CP03 + }) + } ElseIf (LGreaterEqual (\PCNT, 2)) { + Return (Package () + { + _PR.CP00, + _PR.CP01 + }) + } Else { + Return (Package () + { + _PR.CP00 + }) + } +} diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 2ef5031..6a8a7dd 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -26,8 +26,13 @@ External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { - /* Nothing here yet, folks */ + /* Miscellaneous */ Offset (0x00), + PCNT, 8, // 0x01 - Processor Count + PPCM, 8, // 0x02 - Max PPC State + LIDS, 8, // 0x03 - LID State + PWRS, 8, // 0x04 - AC Power State + DPTE, 8, // 0x05 - Enable DPTF
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/acpi/lpc.asl b/src/soc/intel/apollolake/acpi/lpc.asl new file mode 100644 index 0000000..749daf7 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/lpc.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel LPC Bus Device - 0:1f.0 */ + +Device (LPCB) +{ + Name (_ADR, 0x001f0000) +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 9409d5e..44c440e 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -27,3 +27,6 @@ #include "gpio.asl"
#include "xhci.asl" + +/* LPC */ +#include "lpc.asl" diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 8b3a3af..4768aaa 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,7 +28,12 @@
struct global_nvs_t { /* Miscellaneous */ - uint8_t unused[256]; + uint8_t pcnt; /* 0x01 - Processor Count */ + uint8_t ppcm; /* 0x02 - Max PPC State */ + uint8_t lids; /* 0x03 - LID State */ + uint8_t pwrs; /* 0x04 - AC Power State */ + uint8_t dpte; /* 0x05 - Enable DPTF */ + uint8_t unused[251];
/* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;
-
Shaunak Saha