Change in coreboot[master]: soc/amd/cezanne: Fill out pci devices in chipset.cb - coreboot-gerrit

1 Mar 2021


      Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Mathew King, Angel Pons.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51045 )
Change subject: soc/amd/cezanne: Fill out pci devices in chipset.cb
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Patch Set 9: Code-Review+2
(1 comment)
Patchset:
PS9:
...
The PPR shows  […]
from chapter 1 (processor overview) of the ppr: "Two SATA controllers supporting x2 lanes of SATA Gen1/Gen2/Gen3". i'm ok with doing that in a separate patch, since it's not used at the moment anyway
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Iecc75afd7a914651ca15b811163d3559bf73ac9b
Gerrit-Change-Number: 51045
Gerrit-PatchSet: 9
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