Change in coreboot[master]: commonlib/mem_pool: Allow configuring the alignment

[Raul Rangel (Code Review)]

Attention is currently required from: Furquan Shaikh, Julius Werner, Angel Pons, Karthik Ramasubramanian.
Hello build bot (Jenkins), Furquan Shaikh, Julius Werner, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/56580

to look at the new patch set (#8).

Change subject: commonlib/mem_pool: Allow configuring the alignment
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commonlib/mem_pool: Allow configuring the alignment

AMD platforms require the destination to be 64 byte aligned in order to
use the SPI DMA controller. This is enforced by the destination address
register because the first 6 bits are marked as reserved.

This change adds an option to the mem_pool so the alignment can be
configured.

BUG=b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel 
Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075
---
M src/commonlib/include/commonlib/mem_pool.h
M src/commonlib/mem_pool.c
M src/lib/cbfs.c
3 files changed, 16 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/56580/8