build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21547 )
Change subject: soc/intel/skylake: Add config for enabling LTR for PCIe Root port
......................................................................
Patch Set 1: Verified+1
Build Successful
https://qa.coreboot.org/job/coreboot-checkpatch/15716/ : SUCCESS
https://qa.coreboot.org/job/coreboot-gerrit/60512/ : SUCCESS
--
To view, visit
https://review.coreboot.org/21547
To unsubscribe, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Ica97faa78fcd991dad63ae54d2ada82194b4202a
Gerrit-Change-Number: 21547
Gerrit-PatchSet: 1
Gerrit-Owner: Rizwan Qureshi
rizwan.qureshi@intel.com
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-Reviewer: Rajat Jain
rajatja@google.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Comment-Date: Fri, 15 Sep 2017 21:30:41 +0000
Gerrit-HasComments: No