New patch to review for coreboot: cpu/qemu-x86/romstage_entry.inc: Remove redunant cache-as-ram code

[Alexandru Gagniuc]

Alexandru Gagniuc ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12878

-gerrit

commit b8dafe6081ce13287a3b724acf23cd6113c2becb
Author: Alexandru Gagniuc 
Date:   Fri Jan 8 22:51:21 2016 -0800

cpu/qemu-x86/romstage_entry.inc: Remove redunant cache-as-ram code

This CPU doesn't use cache-as-ram; however, since it uses a C
    environment bootblock, any such setup would have to be handled in the
    bootblock anyway.
    Ramstage is succesfully loaded and executed with this change.

Change-Id: Ib9a70fed933ac484f8a5632b6b8f1ab9f69a9ae0
    Signed-off-by: Alexandru Gagniuc 
---
 src/cpu/qemu-x86/romstage_entry.inc | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/src/cpu/qemu-x86/romstage_entry.inc b/src/cpu/qemu-x86/romstage_entry.inc
index fcd2d3b..c930fdc 100644
--- a/src/cpu/qemu-x86/romstage_entry.inc
+++ b/src/cpu/qemu-x86/romstage_entry.inc
@@ -29,15 +29,7 @@

cache_as_ram:
    post_code(0x20)
-       /* Clear the cache memory region. This will also fill up the cache */
-	movl	$CACHE_AS_RAM_BASE, %esi
-	movl	%esi, %edi
-	movl	$(CACHE_AS_RAM_SIZE >> 2), %ecx
-	// movl	$0x23322332, %eax
-	xorl	%eax, %eax
-	rep	stosl

-	post_code(0x21)
    /* Set up the stack pointer. */
    movl	$(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax
    movl	%eax, %esp