Change in coreboot[master]: mb/google/brya/variants/primus: disable LTR for PCIe-eMMC bridge

[Casper Chang (Code Review)]

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58831 )

Change subject: mb/google/brya/variants/primus: disable LTR for PCIe-eMMC bridge
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mb/google/brya/variants/primus: disable LTR for PCIe-eMMC bridge

disable LTR for PCIe-eMMC bridge

BUG=b:204469567
TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed

Signed-off-by: Casper Chang 
Change-Id: I7236fc7f3318d07f0d9e9d9da7cd463ef3dde1a0
---
M src/mainboard/google/brya/variants/primus/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/58831/1

diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index c4debb4..8db2ddb 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -154,7 +154,7 @@
    		register "pch_pcie_rp[PCH_RP(9)]" = "{
    			.clk_src = 0,
    			.clk_req = 0,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.flags = PCIE_RP_AER,
    		}"
    	end	#PCIE9-12 SSD
    	device ref i2c0 on