Change in coreboot[master]: Enable TCSS DMA0 and DMA1 for TGL RVP platform

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John Zhao (Code Review)

14 May 2020 14 May '20

1:34 a.m.

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41386 )

Change subject: Enable TCSS DMA0 and DMA1 for TGL RVP platform ......................................................................

Enable TCSS DMA0 and DMA1 for TGL RVP platform

This explicitly enables both of TCSS DMA0 and DMA1 controllers from TGL RVP platform devicetree setting.

BUG=:b:146624360 TEST=Built and booted on TGL RVP.

Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 16 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/41386/1

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 82f358e..8992722 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -110,8 +110,14 @@ }"

# TCSS USB3 + register "TcssXhciEn" = "1" + register "TcssXdciEn" = "0" register "TcssAuxOri" = "0"

+ # TCSS DMA + register "TcssDma0En" = "1" + register "TcssDma1En" = "1" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -158,8 +164,8 @@ device pci 0a.0 off end # Crash-log SRAM 0x9A0D device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 off end # TBT DMA0 0x9A1B - device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0d.2 on end # TBT DMA0 0x9A1B + device pci 0d.3 on end # TBT DMA1 0x9A1D device pci 0e.0 on end # VMD 0x9A0B

# From PCH EDS(576591) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fec2fef..6839965 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -106,8 +106,14 @@ }"

# TCSS USB3 + register "TcssXhciEn" = "1" + register "TcssXdciEn" = "0" register "TcssAuxOri" = "0"

+ # TCSS DMA + register "TcssDma0En" = "1" + register "TcssDma1En" = "1" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -154,8 +160,8 @@ device pci 0a.0 off end # Crash-log SRAM 0x9A0D device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 off end # TBT DMA0 0x9A1B - device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0d.2 on end # TBT DMA0 0x9A1B + device pci 0d.3 on end # TBT DMA1 0x9A1D device pci 0e.0 on end # VMD 0x9A0B

# From PCH EDS(576591)

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John Zhao (Code Review)

14 May 14 May

1:43 a.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS DMA0 and DMA1 for TGL RVP platform

Hello build bot (Jenkins), Wonkyu Kim, Caveh Jalali, Nick Vaccaro,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41386

to look at the new patch set (#2).

Change subject: mb/intel/tglrvp: Enable TCSS DMA0 and DMA1 for TGL RVP platform ......................................................................

mb/intel/tglrvp: Enable TCSS DMA0 and DMA1 for TGL RVP platform

This explicitly enables both of TCSS DMA0 and DMA1 controllers from TGL RVP platform devicetree setting.

BUG=:b:146624360 TEST=Built and booted on TGL RVP.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/41386/2

Nick Vaccaro (Code Review)

15 May 15 May

2:45 a.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS DMA0 and DMA1 for TGL RVP platform

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41386 )

Change subject: mb/intel/tglrvp: Enable TCSS DMA0 and DMA1 for TGL RVP platform ......................................................................

Patch Set 2: Code-Review+1

John Zhao (Code Review)

26 May 26 May

8:01 p.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS DMA0 and DMA1 for TGL RVP platform

Hello build bot (Jenkins), Wonkyu Kim, Caveh Jalali, Nick Vaccaro,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41386

to look at the new patch set (#5).

Change subject: mb/intel/tglrvp: Enable TCSS DMA0 and DMA1 for TGL RVP platform ......................................................................

mb/intel/tglrvp: Enable TCSS DMA0 and DMA1 for TGL RVP platform

This explicitly enables Tcss xHci, PCIe root ports and DMA controllers from TGL RVP platform devicetree setting.

BUG=:b:146624360 TEST=Built and booted on TGL RVP.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/41386/5

John Zhao (Code Review)

8:03 p.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS xHci, PCIe root ports and DMA controllers

Hello build bot (Jenkins), Wonkyu Kim, Caveh Jalali, Nick Vaccaro,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41386

to look at the new patch set (#6).

Change subject: mb/intel/tglrvp: Enable TCSS xHci, PCIe root ports and DMA controllers ......................................................................

mb/intel/tglrvp: Enable TCSS xHci, PCIe root ports and DMA controllers

This explicitly enables Tcss xHci, PCIe root ports and DMA controllers from TGL RVP platform devicetree setting.

BUG=:b:146624360 TEST=Built and booted on TGL RVP.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/41386/6

Wonkyu Kim (Code Review)

8:10 p.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS xHci, PCIe root ports and DMA controllers

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41386 )

Change subject: mb/intel/tglrvp: Enable TCSS xHci, PCIe root ports and DMA controllers ......................................................................

Patch Set 6: Code-Review+1

Paul Menzel (Code Review)

27 May 27 May

1:17 p.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS xHci, PCIe root ports and DMA controllers

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41386 )

Change subject: mb/intel/tglrvp: Enable TCSS xHci, PCIe root ports and DMA controllers ......................................................................

Patch Set 6:

(2 comments)

https://review.coreboot.org/c/coreboot/+/41386/6//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/41386/6//COMMIT_MSG@7 PS6, Line 7: xHci xHCI

https://en.wikipedia.org/wiki/Extensible_Host_Controller_Interface

https://review.coreboot.org/c/coreboot/+/41386/6//COMMIT_MSG@9 PS6, Line 9: xHci Ditto.

-- To view, visit https://review.coreboot.org/c/coreboot/+/41386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce Gerrit-Change-Number: 41386 Gerrit-PatchSet: 6 Gerrit-Owner: John Zhao john.zhao@intel.com Gerrit-Reviewer: Caveh Jalali caveh@chromium.org Gerrit-Reviewer: Duncan Laurie dlaurie@chromium.org Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 27 May 2020 11:17:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

John Zhao (Code Review)

6:07 p.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers

Hello build bot (Jenkins), Shaunak Saha, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Nick Vaccaro, Srinidhi N Kaushik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41386

to look at the new patch set (#7).

Change subject: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers ......................................................................

mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers

This explicitly enables TCSS xHCI, PCIe root ports and DMA controllers from TGL RVP platform devicetree setting.

BUG=:b:146624360 TEST=Built and booted on TGL RVP.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/41386/7

-- To view, visit https://review.coreboot.org/c/coreboot/+/41386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce Gerrit-Change-Number: 41386 Gerrit-PatchSet: 7 Gerrit-Owner: John Zhao john.zhao@intel.com Gerrit-Reviewer: Caveh Jalali caveh@chromium.org Gerrit-Reviewer: Duncan Laurie dlaurie@chromium.org Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

John Zhao (Code Review)

6:08 p.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41386 )

Change subject: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers ......................................................................

Patch Set 7:

(2 comments)

https://review.coreboot.org/c/coreboot/+/41386/6//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/41386/6//COMMIT_MSG@7 PS6, Line 7: xHci

...

xHCI […]

Ack

https://review.coreboot.org/c/coreboot/+/41386/6//COMMIT_MSG@9 PS6, Line 9: xHci

...

Ditto.

Ack

-- To view, visit https://review.coreboot.org/c/coreboot/+/41386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce Gerrit-Change-Number: 41386 Gerrit-PatchSet: 7 Gerrit-Owner: John Zhao john.zhao@intel.com Gerrit-Reviewer: Caveh Jalali caveh@chromium.org Gerrit-Reviewer: Duncan Laurie dlaurie@chromium.org Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 27 May 2020 16:08:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: comment

John Zhao (Code Review)

28 May 28 May

8:51 a.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers

Hello build bot (Jenkins), Shaunak Saha, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Nick Vaccaro, Srinidhi N Kaushik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41386

to look at the new patch set (#8).

Change subject: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers ......................................................................

mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers

This explicitly enables TCSS xHCI, PCIe root ports and DMA controllers from TGL RVP platform devicetree setting.

BUG=:b:146624360 TEST=Built and booted on TGL RVP.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/41386/8

-- To view, visit https://review.coreboot.org/c/coreboot/+/41386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce Gerrit-Change-Number: 41386 Gerrit-PatchSet: 8 Gerrit-Owner: John Zhao john.zhao@intel.com Gerrit-Reviewer: Caveh Jalali caveh@chromium.org Gerrit-Reviewer: Duncan Laurie dlaurie@chromium.org Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Wonkyu Kim (Code Review)

8:57 a.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41386 )

Change subject: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers ......................................................................

Patch Set 8: Code-Review+1

-- To view, visit https://review.coreboot.org/c/coreboot/+/41386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce Gerrit-Change-Number: 41386 Gerrit-PatchSet: 8 Gerrit-Owner: John Zhao john.zhao@intel.com Gerrit-Reviewer: Caveh Jalali caveh@chromium.org Gerrit-Reviewer: Duncan Laurie dlaurie@chromium.org Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Thu, 28 May 2020 06:57:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Wonkyu Kim (Code Review)

1 Jun 1 Jun

8:15 p.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41386 )

Change subject: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers ......................................................................

Patch Set 8: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/41386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce Gerrit-Change-Number: 41386 Gerrit-PatchSet: 8 Gerrit-Owner: John Zhao john.zhao@intel.com Gerrit-Reviewer: Caveh Jalali caveh@chromium.org Gerrit-Reviewer: Duncan Laurie dlaurie@chromium.org Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Mon, 01 Jun 2020 18:15:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Duncan Laurie (Code Review)

2 Jun 2 Jun

10:14 p.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers

Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41386 )

Change subject: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers ......................................................................

mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers

This explicitly enables TCSS xHCI, PCIe root ports and DMA controllers from TGL RVP platform devicetree setting.

BUG=:b:146624360 TEST=Built and booted on TGL RVP.

Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/41386 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 20 insertions(+), 18 deletions(-)

Approvals: build bot (Jenkins): Verified Wonkyu Kim: Looks good to me, approved

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 7669b18..582ee12 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -109,13 +109,14 @@ [PchSerialIoIndexUART2] = PchSerialIoPci, }"

+ # TCSS USB3 + register "TcssXhciEn" = "1" + register "TcssAuxOri" = "0" + # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" register "TcssD3ColdEnable" = "1"

- # TCSS USB3 - register "TcssAuxOri" = "0" - #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -153,17 +154,17 @@ device pci 04.0 on end # DPTF 0x9A03 device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 - device pci 07.0 off end # TBT_PCIe0 0x9A23 - device pci 07.1 off end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 + device pci 07.0 on end # TBT_PCIe0 0x9A23 + device pci 07.1 on end # TBT_PCIe1 0x9A25 + device pci 07.2 on end # TBT_PCIe2 0x9A27 + device pci 07.3 on end # TBT_PCIe3 0x9A29 device pci 08.0 off end # GNA 0x9A11 device pci 09.0 off end # NPK 0x9A33 device pci 0a.0 off end # Crash-log SRAM 0x9A0D device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 off end # TBT DMA0 0x9A1B - device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0d.2 on end # TBT DMA0 0x9A1B + device pci 0d.3 on end # TBT DMA1 0x9A1D device pci 0e.0 off end # VMD 0x9A0B

# From PCH EDS(576591) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 1d1d6dc..d15da30 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -105,13 +105,14 @@ [PchSerialIoIndexUART2] = PchSerialIoPci, }"

+ # TCSS USB3 + register "TcssXhciEn" = "1" + register "TcssAuxOri" = "0" + # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" register "TcssD3ColdEnable" = "1"

- # TCSS USB3 - register "TcssAuxOri" = "0" - #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -149,17 +150,17 @@ device pci 04.0 on end # DPTF 0x9A03 device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 - device pci 07.0 off end # TBT_PCIe0 0x9A23 - device pci 07.1 off end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 + device pci 07.0 on end # TBT_PCIe0 0x9A23 + device pci 07.1 on end # TBT_PCIe1 0x9A25 + device pci 07.2 on end # TBT_PCIe2 0x9A27 + device pci 07.3 on end # TBT_PCIe3 0x9A29 device pci 08.0 off end # GNA 0x9A11 device pci 09.0 off end # NPK 0x9A33 device pci 0a.0 off end # Crash-log SRAM 0x9A0D device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 off end # TBT DMA0 0x9A1B - device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0d.2 on end # TBT DMA0 0x9A1B + device pci 0d.3 on end # TBT DMA1 0x9A1D device pci 0e.0 off end # VMD 0x9A0B

# From PCH EDS(576591)

-- To view, visit https://review.coreboot.org/c/coreboot/+/41386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce Gerrit-Change-Number: 41386 Gerrit-PatchSet: 9 Gerrit-Owner: John Zhao john.zhao@intel.com Gerrit-Reviewer: Caveh Jalali caveh@chromium.org Gerrit-Reviewer: Duncan Laurie dlaurie@chromium.org Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: merged

9elements QA (Code Review)

10:28 p.m.

New subject: Change in coreboot[master]: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41386 )

Change subject: mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers ......................................................................

Patch Set 9:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4710 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4709 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4708 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4707

Please note: This test is under development and might not be accurate at all!

-- To view, visit https://review.coreboot.org/c/coreboot/+/41386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce Gerrit-Change-Number: 41386 Gerrit-PatchSet: 9 Gerrit-Owner: John Zhao john.zhao@intel.com Gerrit-Reviewer: Caveh Jalali caveh@chromium.org Gerrit-Reviewer: Duncan Laurie dlaurie@chromium.org Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: 9elements QA hardwaretestrobot@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 02 Jun 2020 20:28:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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9elements QA (Code Review)
Duncan Laurie (Code Review)
John Zhao (Code Review)
Nick Vaccaro (Code Review)
Paul Menzel (Code Review)
Wonkyu Kim (Code Review)