Change in coreboot[master]: amd/common/psp: Enable PSP command register once

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22846

Change subject: amd/common/psp: Enable PSP command register once
......................................................................

amd/common/psp: Enable PSP command register once

Reduce the number of times the PSP's bus-mastering and memory
access is enabled.  Only write the command register once per stage
and leave it enabled.

Change-Id: I7e29a3935df94d16de90b28ff78449d23fe01666
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/common/block/psp/psp.c
1 file changed, 32 insertions(+), 35 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/22846/1

diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c
index 5aedfc1..c1174bc 100644
--- a/src/soc/amd/common/block/psp/psp.c
+++ b/src/soc/amd/common/block/psp/psp.c
@@ -14,6 +14,7 @@
  */

#include <arch/io.h>
+#include <arch/early_variables.h>
 #include <cbfs.h>
 #include <region_file.h>
 #include <timer.h>
@@ -49,6 +50,20 @@
    }
 }

+static int master_enabled CAR_GLOBAL = 0;
+
+static void enable_master(void)
+{
+	u32 command_reg;
+
+	if (!master_enabled) {
+		command_reg = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
+		command_reg |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+		pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, command_reg);
+		master_enabled = 1;
+	}
+}
+
 static struct psp_mbox *get_mbox_address(void)
 {
    UINT32 base; /* UINT32 for compatibility with PspBaseLib */
@@ -63,6 +78,7 @@
    if (!bar3_status)
    	return NULL;

+	enable_master();
    baseptr = base;
    return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE);
 }
@@ -122,56 +138,37 @@

static int send_psp_command(u32 command, void *buffer)
 {
-	u32 command_reg;
-	int status = 0;
-
    struct psp_mbox *mbox = get_mbox_address();
    if (!mbox)
    	return -PSPSTS_NOBASE;

-	command_reg = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
-	pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, command_reg |
-				PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
    /* check for PSP error conditions */
-	if (rd_mbox_sts(mbox) & STATUS_HALT) {
-		status = -PSPSTS_HALTED;
-		goto exit;
-	}
-	if (rd_mbox_sts(mbox) & STATUS_RECOVERY) {
-		status = -PSPSTS_RECOVERY;
-		goto exit;
-	}
+	if (rd_mbox_sts(mbox) & STATUS_HALT)
+		return -PSPSTS_HALTED;
+
+	if (rd_mbox_sts(mbox) & STATUS_RECOVERY)
+		return -PSPSTS_RECOVERY;

/* PSP must be finished with init and ready to accept a command */
-	if (wait_initialized(mbox)) {
-		status = -PSPSTS_INIT_TIMEOUT;
-		goto exit;
-	}
-	if (wait_command(mbox)) {
-		status = -PSPSTS_CMD_TIMEOUT;
-		goto exit;
-	}
+	if (wait_initialized(mbox))
+		return -PSPSTS_INIT_TIMEOUT;
+
+	if (wait_command(mbox))
+		return -PSPSTS_CMD_TIMEOUT;

/* set address of command-response buffer and write command register */
    wr_mbox_cmd_resp(mbox, buffer);
    wr_mbox_cmd(mbox, command);

/* PSP clears command register when complete */
-	if (wait_command(mbox)) {
-		status = -PSPSTS_CMD_TIMEOUT;
-		goto exit;
-	}
+	if (wait_command(mbox))
+		return -PSPSTS_CMD_TIMEOUT;

/* check delivery status */
-	if (rd_mbox_sts(mbox) & (STATUS_ERROR | STATUS_TERMINATED)) {
-		status = -PSPSTS_SEND_ERROR;
-		goto exit;
-	}
-exit:
-	/* restore command register to original value */
-	pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, command_reg);
-	return status;
+	if (rd_mbox_sts(mbox) & (STATUS_ERROR | STATUS_TERMINATED))
+		return -PSPSTS_SEND_ERROR;
+
+	return 0;
 }

/*