[S] Change in coreboot[master]: drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs

[Subrata Banik (Code Review)]

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nico Huber, Paul Menzel, Raul Rangel.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77556?usp=email )

Change subject: drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs
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Patch Set 7:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/77556/comment/39afba70_048049d2 :
PS3, Line 43: +--------------------+--------------------------+--------------------------+-------------------------+
> Just because it's not an issue in one program's git log function doesn't mean it isn't in others. There are lots of different tools and there's a reason for the rule to wrap at 72/75 characters.

I have updated the commit msg w/ latest patch set. can you please take a look ?

Commit Message:

https://review.coreboot.org/c/coreboot/+/77556/comment/7e09cd55_e7dd7ff0 :
PS6, Line 21: cache post in FSP-S (at ramstage). Hence, this patch provides an API to
> Nit: this sentence needs to be  rephrased.

Acknowledged