Change in coreboot[master]: Veyron: add Hynix H9CCNNNBKTMLBR-NTD ddr with RAMID '00Z1'
Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/29366 ) Change subject: Veyron: add Hynix H9CCNNNBKTMLBR-NTD ddr with RAMID '00Z1' ...................................................................... Veyron: add Hynix H9CCNNNBKTMLBR-NTD ddr with RAMID '00Z1' Confirm with RK, H9CCNNNBKTMLBR-NTD uses this sdram config. sdram-lpddr3-hynix-4GB.inc BUG=b:117967129 BRANCH=master TEST=None Change-Id: I98afc33fd2cb61343be0dcdc007add75bee9c2af Signed-off-by: Loop_Wu <Loop_Wu@asus.com> Reviewed-on: https://review.coreboot.org/29366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> --- M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/sdram_configs.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c index 88c0a69..ee8d4c1 100644 --- a/src/mainboard/google/veyron/sdram_configs.c +++ b/src/mainboard/google/veyron/sdram_configs.c @@ -40,7 +40,7 @@ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 000Z */ #include "sdram_inf/sdram-lpddr3-micron-2GB-D2.inc" /* ram_code = 001Z */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z0 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z1 */ +#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 00Z1 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 00ZZ */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 010Z */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 011Z */ diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index 88c0a69..ee8d4c1 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -40,7 +40,7 @@ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 000Z */ #include "sdram_inf/sdram-lpddr3-micron-2GB-D2.inc" /* ram_code = 001Z */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z0 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z1 */ +#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 00Z1 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 00ZZ */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 010Z */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 011Z */ -- To view, visit https://review.coreboot.org/29366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I98afc33fd2cb61343be0dcdc007add75bee9c2af Gerrit-Change-Number: 29366 Gerrit-PatchSet: 2 Gerrit-Owner: Loop Wu <Loop_Wu@asus.com> Gerrit-Reviewer: HL - <hl@rockchip.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner@chromium.org> Gerrit-Reviewer: Loop Wu <Loop_Wu@asus.com> Gerrit-Reviewer: Philip Chen <philipchen@chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
participants (1)
-
Julius Werner (Code Review)