Change in coreboot[master]: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0

[John Zhao (Code Review)]

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50086 )

Change subject: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0
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soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0

A minimum of 100ms delay is required before sending a configuration
request to the downstream components. Since the kernel already adds
100ms, this change drops the extra 100ms delay in TBT PCIe root ports
_PS0 method in order to improve resume time.

BUG=b:177519081
TEST=Boot to kernel and validated various tests on Voxel.

Signed-off-by: John Zhao 
Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304
---
M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
1 file changed, 0 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/50086/1

diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
index 08d8900..39180f7 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
@@ -196,8 +196,6 @@
    If (PMEX == 1) {
    	PMEX = 0  /* Disable Power Management SCI */
    }
-
-	Sleep(100)  /* Wait for 100ms before return to OS starts any OS activities. */
 }

Method (_PS3, 0, Serialized)