[M] Change in coreboot[main]: [test][Do not merge] Revert "arch/x86: Reduce max phys address size f...

[Ronak Kanabar (Code Review)]

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79399?usp=email )

Change subject: [test][Do not merge] Revert "arch/x86: Reduce max phys address size for Intel TME capable SoCs"
......................................................................

[test][Do not merge] Revert "arch/x86: Reduce max phys address size for Intel TME capable SoCs"

This reverts commit 1eff77bc59b77735872e675a8df4f059245e4be7.

Change-Id: If4249b65f4294b38b0721d1a3ba577e87766f547
---
M src/arch/x86/cpu_common.c
M src/arch/x86/include/arch/cpu.h
M src/cpu/intel/common/Makefile.inc
M src/cpu/intel/common/common_init.c
M src/include/cpu/intel/msr.h
5 files changed, 2 insertions(+), 49 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/79399/1

diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c
index 0242dce..ebd13c9 100644
--- a/src/arch/x86/cpu_common.c
+++ b/src/arch/x86/cpu_common.c
@@ -49,11 +49,8 @@
    if (!(cpu_have_cpuid()))
    	return 32;

-	if (cpu_cpuid_extended_level() >= 0x80000008) {
-		int size = cpuid_eax(0x80000008) & 0xff;
-		size -= get_reserved_phys_addr_bits();
-		return size;
-	}
+	if (cpu_cpuid_extended_level() >= 0x80000008)
+		return cpuid_eax(0x80000008) & 0xff;

if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
    	return 36;
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 0c4decf..aca0d46 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -329,15 +329,4 @@
  */
 bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info);

-#if CONFIG(RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT)
-unsigned int get_reserved_phys_addr_bits(void);
-#else
-/* Default implementation */
-static inline unsigned int get_reserved_phys_addr_bits(void)
-{
-	/* Default implementation */
-	return 0;
-}
-#endif
-
 #endif /* ARCH_CPU_H */
diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc
index 8b247ab..c4ac57e 100644
--- a/src/cpu/intel/common/Makefile.inc
+++ b/src/cpu/intel/common/Makefile.inc
@@ -1,8 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only

-bootblock-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
 romstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
-postcar-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON) += hyperthreading.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON_VOLTAGE) += voltage.c
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index 83a21e0..f8608ae 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -238,31 +238,3 @@
    cpuid_regs = cpuid_ext(CPUID_STRUCT_EXTENDED_FEATURE_FLAGS, 0x0);
    return (cpuid_regs.ecx & CPUID_EXT_FEATURE_TME_SUPPORTED);
 }
-
-/*
- * Get number of address bits used by Total Memory Encryption (TME)
- *
- * Returns TME_ACTIVATE[MK_TME_KEYID_BITS] (MSR 0x982 Bits[32-35]).
- *
- * NOTE: This function should be called after MK-TME features has been
- * configured in the MSRs according to the capabilities and platform
- * configuration. For instance, after FSP-M.
- */
-static unsigned int get_tme_keyid_bits(void)
-{
-	msr_t msr;
-
-	msr = rdmsr(MSR_TME_ACTIVATE);
-	return msr.hi & TME_ACTIVATE_HI_KEYID_BITS_MASK;
-}
-
-unsigned int get_reserved_phys_addr_bits(void)
-{
-	if (CONFIG_CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS)
-		return CONFIG_CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS;
-
-	if (!is_tme_supported())
-		return 0;
-
-	return get_tme_keyid_bits();
-}
diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h
index 75c12a8..8efe4e2 100644
--- a/src/include/cpu/intel/msr.h
+++ b/src/include/cpu/intel/msr.h
@@ -33,7 +33,4 @@

#define MSR_PKG_C10_RESIDENCY	0x632

-#define MSR_TME_ACTIVATE			0x982
-#define  TME_ACTIVATE_HI_KEYID_BITS_MASK	0xf
-
 #endif /* CPU_INTEL_MSR_H */