[M] Change in blobs[main]: soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/blobs/+/85110?usp=email )

Change subject: soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration
......................................................................

soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration

This blob includes both full calibration and fast calibration flow.

BUG=b:317009620
TEST=DRAM calibration pass.

Change-Id: I726f1cdadb99ba160cf20e65a6eacaa81998d043
Signed-off-by: Crystal Guo 
---
M soc/mediatek/mt8196/README.md
A soc/mediatek/mt8196/dram.elf
A soc/mediatek/mt8196/dram.elf.md5
A soc/mediatek/mt8196/dram_release_notes.txt
4 files changed, 107 insertions(+), 0 deletions(-)

Approvals:
  Yidi Lin: Looks good to me, approved
  Yu-Ping Wu: Verified; Looks good to me, approved

diff --git a/soc/mediatek/mt8196/README.md b/soc/mediatek/mt8196/README.md
index bdc850b..7f83d7a 100644
--- a/soc/mediatek/mt8196/README.md
+++ b/soc/mediatek/mt8196/README.md
@@ -3,6 +3,7 @@
 - sspm.bin
 - dpm.dm
 - dpm.pm
+- dram.elf

--------------------------------------------------------------------------------
 # MCUPM introduction
@@ -72,3 +73,104 @@
 ```

--------------------------------------------------------------------------------
+# `dram.elf` introduction
+`dram.elf` is an ELF format file, which performs DRAM full calibration, DRAM
+fast calibration and returns the trained calibration parameters to the caller.
+The caller may store the parameters on NOR/NAND or eMMC for faster subsequent
+bootups.
+
+## Who uses it
+Coreboot loads `dram.elf` during the first bootup if no valid DRAM parameters
+are found on NOR/NAND or eMMC.
+
+## How to load `dram.elf`
+Coreboot locates `dram.elf` file, locates the entry point `_start`,
+passes a `dramc_param` struct argument `dparam` to it, and calls
+`_start(&dparam)` to execute `dram.elf`.
+
+## Parameters
+```
+struct dramc_param {
+	struct dramc_param_header header;
+	void (*do_putc)(unsigned char c);
+	struct dramc_data dramc_datas;
+};
+```
+
+Below shows the internal structure of `dramc_param`:
+```
+struct dramc_param_header {
+	u16 version;	/* DRAMC_PARAM_HEADER_VERSION, set in coreboot */
+	u16 size;	/* size of whole dramc_param, set in coreboot */
+	u16 status;	/* DRAMC_PARAM_STATUS_CODES, set in dram blob */
+	u16 flags;	/* DRAMC_PARAM_FLAG, set in dram blob */
+	u16 config;	/* DRAMC_PARAM_CONFIG, set in coreboot */
+};
+
+struct sdram_params {
+	/* rank, cbt */
+	u32 rank_num;
+	u32 dram_cbt_mode;
+
+	u16 delay_cell_timex100;
+	u8 u18ph_dly;
+
+	/* duty */
+	s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
+	s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+	s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+	.......
+	.......
+};
+
+struct ddr_mrr_info {
+	u16 mr5_vendor_id;
+	u16 mr6_revision_id;
+	u16 mr7_revision_id;
+	u64 mr8_density[RANK_MAX];
+	u32 rank_nums;
+	u8 die_num[RANK_MAX];
+};
+
+struct emi_mdl {
+	u32 cona_val;
+	u32 conh_val;
+	u32 conf_val;
+	u32 chn_cona_val;
+};
+
+struct sdram_info {
+	u32 ddr_type;		/* SDRAM_DDR_TYPE */
+	u32 ddr_geometry;	/* SDRAM_DDR_GEOMETRY_TYPE */
+};
+
+struct ddr_base_info {
+	u32 config_dvfs;		/* SDRAM_DVFS_FLAG */
+	struct sdram_info sdram;
+	u32 voltage_type;		/* SDRAM_VOLTAGE_TYPE */
+	u32 support_ranks;
+	u64 rank_size[RANK_MAX];
+	struct emi_mdl emi_config;
+	DRAM_CBT_MODE_T cbt_mode[RANK_MAX];
+	struct ddr_mrr_info mrr_info;
+	u32 data_rate;
+};
+
+struct dramc_data {
+	struct ddr_base_info ddr_info;
+	struct sdram_params freq_params[DRAM_DFS_SHU_MAX];
+};
+```
+
+## The output of `dram.elf`
+`dram.elf` configures suitable dramc settings and returns the DRAM parameters.
+Then, Coreboot saves the parameters on the specified firmware flash section:
+`"RW_MRC_CACHE"`.
+
+## Return values
+0 on success; < 0 on failure.
+
+## Version
+`$ strings dram.elf | grep "firmware version"`
+
+--------------------------------------------------------------------------------
diff --git a/soc/mediatek/mt8196/dram.elf b/soc/mediatek/mt8196/dram.elf
new file mode 100644
index 0000000..3faa1cf
--- /dev/null
+++ b/soc/mediatek/mt8196/dram.elf
Binary files differ
diff --git a/soc/mediatek/mt8196/dram.elf.md5 b/soc/mediatek/mt8196/dram.elf.md5
new file mode 100644
index 0000000..cb044a4
--- /dev/null
+++ b/soc/mediatek/mt8196/dram.elf.md5
@@ -0,0 +1 @@
+f28bedae7529a3be011fb0a6bb478c94 *dram.elf
diff --git a/soc/mediatek/mt8196/dram_release_notes.txt b/soc/mediatek/mt8196/dram_release_notes.txt
new file mode 100644
index 0000000..7f6b7a2
--- /dev/null
+++ b/soc/mediatek/mt8196/dram_release_notes.txt
@@ -0,0 +1,4 @@
+# 0.3.0
+
+1. An official build from ChromeOS version 16093.0.0.
+   Protocol (params header) version: 3