Change in coreboot[master]: soc/intel/cannonlake: Add debugging of a number of FSPM parameters
Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35802 )
Change subject: soc/intel/cannonlake: Add debugging of a number of FSPM parameters ......................................................................
soc/intel/cannonlake: Add debugging of a number of FSPM parameters
This implements soc_display_fspm_upd_params for soc/intel/cannonlake
Some parameters are available only on Coffee Lake FSP or Comet Lake FSP
Tested on System76 galp3-c (Coffee Lake FSP) and System76 galp4 (Comet Lake FSP)
Change-Id: I01c7a07ce7446ff762849c64600e728339a4974f Signed-Of-By: Jeremy Soller jeremy@system76.com --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 313 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35802/1
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index f782f63..af278cf 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -141,3 +141,316 @@ if (!s3wake) save_dimm_info(); } + +void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, + const FSPM_UPD *fspm_new_upd) +{ + const FSP_M_CONFIG *new; + const FSP_M_CONFIG *old; + + old = &fspm_old_upd->FspmConfig; + new = &fspm_new_upd->FspmConfig; + + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + + //TODO: Add more Comet Lake values + fsp_display_upd_value("PlatformMemorySize", 8, + old->PlatformMemorySize, new->PlatformMemorySize); + fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00, + new->MemorySpdPtr00); + fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01, + new->MemorySpdPtr01); + fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10, + new->MemorySpdPtr10); + fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11, + new->MemorySpdPtr11); + fsp_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen, + new->MemorySpdDataLen); + fsp_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0], + new->DqByteMapCh0[0]); + fsp_display_upd_value("DqByteMapCh0[1]", 1, old->DqByteMapCh0[1], + new->DqByteMapCh0[1]); + fsp_display_upd_value("DqByteMapCh0[2]", 1, old->DqByteMapCh0[2], + new->DqByteMapCh0[2]); + fsp_display_upd_value("DqByteMapCh0[3]", 1, old->DqByteMapCh0[3], + new->DqByteMapCh0[3]); + fsp_display_upd_value("DqByteMapCh0[4]", 1, old->DqByteMapCh0[4], + new->DqByteMapCh0[4]); + fsp_display_upd_value("DqByteMapCh0[5]", 1, old->DqByteMapCh0[5], + new->DqByteMapCh0[5]); + fsp_display_upd_value("DqByteMapCh0[6]", 1, old->DqByteMapCh0[6], + new->DqByteMapCh0[6]); + fsp_display_upd_value("DqByteMapCh0[7]", 1, old->DqByteMapCh0[7], + new->DqByteMapCh0[7]); + fsp_display_upd_value("DqByteMapCh0[8]", 1, old->DqByteMapCh0[8], + new->DqByteMapCh0[8]); + fsp_display_upd_value("DqByteMapCh0[9]", 1, old->DqByteMapCh0[9], + new->DqByteMapCh0[9]); + fsp_display_upd_value("DqByteMapCh0[10]", 1, old->DqByteMapCh0[10], + new->DqByteMapCh0[10]); + fsp_display_upd_value("DqByteMapCh0[11]", 1, old->DqByteMapCh0[11], + new->DqByteMapCh0[11]); + fsp_display_upd_value("DqByteMapCh1[0]", 1, old->DqByteMapCh1[0], + new->DqByteMapCh1[0]); + fsp_display_upd_value("DqByteMapCh1[1]", 1, old->DqByteMapCh1[1], + new->DqByteMapCh1[1]); + fsp_display_upd_value("DqByteMapCh1[2]", 1, old->DqByteMapCh1[2], + new->DqByteMapCh1[2]); + fsp_display_upd_value("DqByteMapCh1[3]", 1, old->DqByteMapCh1[3], + new->DqByteMapCh1[3]); + fsp_display_upd_value("DqByteMapCh1[4]", 1, old->DqByteMapCh1[4], + new->DqByteMapCh1[4]); + fsp_display_upd_value("DqByteMapCh1[5]", 1, old->DqByteMapCh1[5], + new->DqByteMapCh1[5]); + fsp_display_upd_value("DqByteMapCh1[6]", 1, old->DqByteMapCh1[6], + new->DqByteMapCh1[6]); + fsp_display_upd_value("DqByteMapCh1[7]", 1, old->DqByteMapCh1[7], + new->DqByteMapCh1[7]); + fsp_display_upd_value("DqByteMapCh1[8]", 1, old->DqByteMapCh1[8], + new->DqByteMapCh1[8]); + fsp_display_upd_value("DqByteMapCh1[9]", 1, old->DqByteMapCh1[9], + new->DqByteMapCh1[9]); + fsp_display_upd_value("DqByteMapCh1[10]", 1, old->DqByteMapCh1[10], + new->DqByteMapCh1[10]); + fsp_display_upd_value("DqByteMapCh1[11]", 1, old->DqByteMapCh1[11], + new->DqByteMapCh1[11]); + fsp_display_upd_value("DqsMapCpu2DramCh0[0]", 1, + old->DqsMapCpu2DramCh0[0], new->DqsMapCpu2DramCh0[0]); + fsp_display_upd_value("DqsMapCpu2DramCh0[1]", 1, + old->DqsMapCpu2DramCh0[1], new->DqsMapCpu2DramCh0[1]); + fsp_display_upd_value("DqsMapCpu2DramCh0[2]", 1, + old->DqsMapCpu2DramCh0[2], new->DqsMapCpu2DramCh0[2]); + fsp_display_upd_value("DqsMapCpu2DramCh0[3]", 1, + old->DqsMapCpu2DramCh0[3], new->DqsMapCpu2DramCh0[3]); + fsp_display_upd_value("DqsMapCpu2DramCh0[4]", 1, + old->DqsMapCpu2DramCh0[4], new->DqsMapCpu2DramCh0[4]); + fsp_display_upd_value("DqsMapCpu2DramCh0[5]", 1, + old->DqsMapCpu2DramCh0[5], new->DqsMapCpu2DramCh0[5]); + fsp_display_upd_value("DqsMapCpu2DramCh0[6]", 1, + old->DqsMapCpu2DramCh0[6], new->DqsMapCpu2DramCh0[6]); + fsp_display_upd_value("DqsMapCpu2DramCh0[7]", 1, + old->DqsMapCpu2DramCh0[7], new->DqsMapCpu2DramCh0[7]); + fsp_display_upd_value("DqsMapCpu2DramCh1[0]", 1, + old->DqsMapCpu2DramCh1[0], new->DqsMapCpu2DramCh1[0]); + fsp_display_upd_value("DqsMapCpu2DramCh1[1]", 1, + old->DqsMapCpu2DramCh1[1], new->DqsMapCpu2DramCh1[1]); + fsp_display_upd_value("DqsMapCpu2DramCh1[2]", 1, + old->DqsMapCpu2DramCh1[2], new->DqsMapCpu2DramCh1[2]); + fsp_display_upd_value("DqsMapCpu2DramCh1[3]", 1, + old->DqsMapCpu2DramCh1[3], new->DqsMapCpu2DramCh1[3]); + fsp_display_upd_value("DqsMapCpu2DramCh1[4]", 1, + old->DqsMapCpu2DramCh1[4], new->DqsMapCpu2DramCh1[4]); + fsp_display_upd_value("DqsMapCpu2DramCh1[5]", 1, + old->DqsMapCpu2DramCh1[5], new->DqsMapCpu2DramCh1[5]); + fsp_display_upd_value("DqsMapCpu2DramCh1[6]", 1, + old->DqsMapCpu2DramCh1[6], new->DqsMapCpu2DramCh1[6]); + fsp_display_upd_value("DqsMapCpu2DramCh1[7]", 1, + old->DqsMapCpu2DramCh1[7], new->DqsMapCpu2DramCh1[7]); + fsp_display_upd_value("RcompResistor[0]", 2, old->RcompResistor[0], + new->RcompResistor[0]); + fsp_display_upd_value("RcompResistor[1]", 2, old->RcompResistor[1], + new->RcompResistor[1]); + fsp_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2], + new->RcompResistor[2]); + fsp_display_upd_value("RcompTarget[0]", 2, old->RcompTarget[0], + new->RcompTarget[0]); + fsp_display_upd_value("RcompTarget[1]", 2, old->RcompTarget[1], + new->RcompTarget[1]); + fsp_display_upd_value("RcompTarget[2]", 2, old->RcompTarget[2], + new->RcompTarget[2]); + fsp_display_upd_value("RcompTarget[3]", 2, old->RcompTarget[3], + new->RcompTarget[3]); + fsp_display_upd_value("RcompTarget[4]", 2, old->RcompTarget[4], + new->RcompTarget[4]); + fsp_display_upd_value("DqPinsInterleaved", 1, old->DqPinsInterleaved, + new->DqPinsInterleaved); + fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig, + new->CaVrefConfig); + fsp_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask); +#if CONFIG(SOC_INTEL_COMETLAKE) + // Value only exists on Comet Lake + fsp_display_upd_value("MrcTimeMeasure", 1, old->MrcTimeMeasure, + new->MrcTimeMeasure); +#endif + fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot, + new->MrcFastBoot); + fsp_display_upd_value("RmtPerTask", 1, old->RmtPerTask, + new->RmtPerTask); + fsp_display_upd_value("TrainTrace", 1, old->TrainTrace, + new->TrainTrace); + fsp_display_upd_value("IedSize", 4, old->IedSize, new->IedSize); + fsp_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize); + fsp_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize); + fsp_display_upd_value("ProbelessTrace", 1, old->ProbelessTrace, + new->ProbelessTrace); + fsp_display_upd_value("GdxcIotSize", 1, old->GdxcIotSize, + new->GdxcIotSize); + fsp_display_upd_value("GdxcMotSize", 1, old->GdxcMotSize, + new->GdxcMotSize); + fsp_display_upd_value("SmbusEnable", 1, old->SmbusEnable, + new->SmbusEnable); + fsp_display_upd_value("SpdAddressTable[0]", 1, old->SpdAddressTable[0], + new->SpdAddressTable[0]); + fsp_display_upd_value("SpdAddressTable[1]", 1, old->SpdAddressTable[1], + new->SpdAddressTable[1]); + fsp_display_upd_value("SpdAddressTable[2]", 1, old->SpdAddressTable[2], + new->SpdAddressTable[2]); + fsp_display_upd_value("SpdAddressTable[3]", 1, old->SpdAddressTable[3], + new->SpdAddressTable[3]); + fsp_display_upd_value("PlatformDebugConsent", 1, + old->PlatformDebugConsent, new->PlatformDebugConsent); + fsp_display_upd_value("DciUsb3TypecUfpDbg", 1, old->DciUsb3TypecUfpDbg, + new->DciUsb3TypecUfpDbg); + fsp_display_upd_value("PchTraceHubMode", 1, old->PchTraceHubMode, + new->PchTraceHubMode); + fsp_display_upd_value("PchTraceHubMemReg0Size", 1, + old->PchTraceHubMemReg0Size, new->PchTraceHubMemReg0Size); + fsp_display_upd_value("PchTraceHubMemReg1Size", 1, + old->PchTraceHubMemReg1Size, new->PchTraceHubMemReg1Size); + // Skip PchPreMemRsvd[9] + fsp_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc, + new->IgdDvmt50PreAlloc); + fsp_display_upd_value("InternalGfx", 1, old->InternalGfx, + new->InternalGfx); + fsp_display_upd_value("ApertureSize", 1, old->ApertureSize, + new->ApertureSize); + fsp_display_upd_value("UserBd", 1, old->UserBd, + new->UserBd); + fsp_display_upd_value("SaGv", 1, old->SaGv, + new->SaGv); + // Skip UnusedUpdSpace0 + fsp_display_upd_value("DdrFreqLimit", 2, old->DdrFreqLimit, + new->DdrFreqLimit); + fsp_display_upd_value("FreqSaGvLow", 2, old->FreqSaGvLow, + new->FreqSaGvLow); +#if ! CONFIG(SOC_INTEL_COMETLAKE) + // Value does not exist on Comet Lake + fsp_display_upd_value("FreqSaGvMid", 2, old->FreqSaGvMid, + new->FreqSaGvMid); +#endif + fsp_display_upd_value("RMT", 1, old->RMT, + new->RMT); + fsp_display_upd_value("DisableDimmChannel0", 1, + old->DisableDimmChannel0, new->DisableDimmChannel0); + fsp_display_upd_value("DisableDimmChannel1", 1, + old->DisableDimmChannel1, new->DisableDimmChannel1); + fsp_display_upd_value("ScramblerSupport", 1, old->ScramblerSupport, + new->ScramblerSupport); + fsp_display_upd_value("SkipMpInit", 1, old->SkipMpInit, + new->SkipMpInit); + // Skip UnusedUpdSpace1[15] + fsp_display_upd_value("SpdProfileSelected", 1, + old->SpdProfileSelected, new->SpdProfileSelected); + fsp_display_upd_value("RefClk", 1, old->RefClk, + new->RefClk); + fsp_display_upd_value("VddVoltage", 2, old->VddVoltage, + new->VddVoltage); + fsp_display_upd_value("Ratio", 1, old->Ratio, + new->Ratio); + fsp_display_upd_value("OddRatioMode", 1, old->OddRatioMode, + new->OddRatioMode); + fsp_display_upd_value("tCL", 1, old->tCL, + new->tCL); + fsp_display_upd_value("tCWL", 1, old->tCWL, + new->tCWL); + fsp_display_upd_value("tRCDtRP", 1, old->tRCDtRP, + new->tRCDtRP); + fsp_display_upd_value("tRRD", 1, old->tRRD, + new->tRRD); + fsp_display_upd_value("tFAW", 2, old->tFAW, + new->tFAW); + fsp_display_upd_value("tRAS", 2, old->tRAS, + new->tRAS); + fsp_display_upd_value("tREFI", 2, old->tREFI, + new->tREFI); + fsp_display_upd_value("tRFC", 2, old->tRFC, + new->tRFC); + fsp_display_upd_value("tRTP", 1, old->tRTP, + new->tRTP); + fsp_display_upd_value("tWR", 1, old->tWR, + new->tWR); + fsp_display_upd_value("NModeSupport", 1, old->NModeSupport, + new->NModeSupport); + fsp_display_upd_value("DllBwEn0", 1, old->DllBwEn0, + new->DllBwEn0); + fsp_display_upd_value("DllBwEn1", 1, old->DllBwEn1, + new->DllBwEn1); + fsp_display_upd_value("DllBwEn2", 1, old->DllBwEn2, + new->DllBwEn2); + fsp_display_upd_value("DllBwEn3", 1, old->DllBwEn3, + new->DllBwEn3); + fsp_display_upd_value("IsvtIoPort", 1, old->IsvtIoPort, + new->IsvtIoPort); + fsp_display_upd_value("CpuTraceHubMode", 1, old->CpuTraceHubMode, + new->CpuTraceHubMode); + fsp_display_upd_value("CpuTraceHubMemReg0Size", 1, + old->CpuTraceHubMemReg0Size, new->CpuTraceHubMemReg0Size); + fsp_display_upd_value("CpuTraceHubMemReg1Size", 1, + old->CpuTraceHubMemReg1Size, new->CpuTraceHubMemReg1Size); + fsp_display_upd_value("PeciC10Reset", 1, old->PeciC10Reset, + new->PeciC10Reset); + fsp_display_upd_value("PeciSxReset", 1, old->PeciSxReset, + new->PeciSxReset); + // Skip UnusedUpdSpace2[4] + fsp_display_upd_value("PchHdaEnable", 1, old->PchHdaEnable, + new->PchHdaEnable); + fsp_display_upd_value("PchIshEnable", 1, old->PchIshEnable, + new->PchIshEnable); + fsp_display_upd_value("HeciTimeouts", 1, old->HeciTimeouts, + new->HeciTimeouts); + // Skip UnusedUpdSpace3 + fsp_display_upd_value("Heci1BarAddress", 4, old->Heci1BarAddress, + new->Heci1BarAddress); + fsp_display_upd_value("Heci2BarAddress", 4, old->Heci2BarAddress, + new->Heci2BarAddress); + fsp_display_upd_value("Heci3BarAddress", 4, old->Heci3BarAddress, + new->Heci3BarAddress); + fsp_display_upd_value("SgDelayAfterPwrEn", 2, old->SgDelayAfterPwrEn, + new->SgDelayAfterPwrEn); + fsp_display_upd_value("SgDelayAfterHoldReset", 2, old->SgDelayAfterHoldReset, + new->SgDelayAfterHoldReset); + fsp_display_upd_value("MmioSizeAdjustment", 2, old->MmioSizeAdjustment, + new->MmioSizeAdjustment); + fsp_display_upd_value("DmiGen3ProgramStaticEq", 1, + old->DmiGen3ProgramStaticEq, new->DmiGen3ProgramStaticEq); + fsp_display_upd_value("Peg0Enable", 1, old->Peg0Enable, + new->Peg0Enable); + fsp_display_upd_value("Peg1Enable", 1, old->Peg1Enable, + new->Peg1Enable); + fsp_display_upd_value("Peg2Enable", 1, old->Peg2Enable, + new->Peg2Enable); + fsp_display_upd_value("Peg3Enable", 1, old->Peg3Enable, + new->Peg3Enable); + fsp_display_upd_value("Peg0MaxLinkSpeed", 1, old->Peg0MaxLinkSpeed, + new->Peg0MaxLinkSpeed); + fsp_display_upd_value("Peg1MaxLinkSpeed", 1, old->Peg1MaxLinkSpeed, + new->Peg1MaxLinkSpeed); + fsp_display_upd_value("Peg2MaxLinkSpeed", 1, old->Peg2MaxLinkSpeed, + new->Peg2MaxLinkSpeed); + fsp_display_upd_value("Peg3MaxLinkSpeed", 1, old->Peg3MaxLinkSpeed, + new->Peg3MaxLinkSpeed); + fsp_display_upd_value("Peg0MaxLinkWidth", 1, old->Peg0MaxLinkWidth, + new->Peg0MaxLinkWidth); + fsp_display_upd_value("Peg1MaxLinkWidth", 1, old->Peg1MaxLinkWidth, + new->Peg1MaxLinkWidth); + fsp_display_upd_value("Peg2MaxLinkWidth", 1, old->Peg2MaxLinkWidth, + new->Peg2MaxLinkWidth); + fsp_display_upd_value("Peg3MaxLinkWidth", 1, old->Peg3MaxLinkWidth, + new->Peg3MaxLinkWidth); + fsp_display_upd_value("Peg0PowerDownUnusedLanes", 1, + old->Peg0PowerDownUnusedLanes, new->Peg0PowerDownUnusedLanes); + fsp_display_upd_value("Peg1PowerDownUnusedLanes", 1, + old->Peg1PowerDownUnusedLanes, new->Peg1PowerDownUnusedLanes); + fsp_display_upd_value("Peg2PowerDownUnusedLanes", 1, + old->Peg2PowerDownUnusedLanes, new->Peg2PowerDownUnusedLanes); + fsp_display_upd_value("Peg3PowerDownUnusedLanes", 1, + old->Peg3PowerDownUnusedLanes, new->Peg3PowerDownUnusedLanes); + fsp_display_upd_value("InitPcieAspmAfterOprom", 1, + old->InitPcieAspmAfterOprom, new->InitPcieAspmAfterOprom); + fsp_display_upd_value("PegDisableSpreadSpectrumClocking", 1, + old->PegDisableSpreadSpectrumClocking, + new->PegDisableSpreadSpectrumClocking); + // Skip UnusedUpdSpace4[3] + //TODO: Offset 0x128 and up +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35802 )
Change subject: soc/intel/cannonlake: Add debugging of a number of FSPM parameters ......................................................................
Patch Set 1:
(198 comments)
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 273: fsp_display_upd_value("MrcTimeMeasure", 1, old->MrcTimeMeasure, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 274: new->MrcTimeMeasure); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 274: new->MrcTimeMeasure); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 302: old->PlatformDebugConsent, new->PlatformDebugConsent); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 302: old->PlatformDebugConsent, new->PlatformDebugConsent); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 308: old->PchTraceHubMemReg0Size, new->PchTraceHubMemReg0Size); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 308: old->PchTraceHubMemReg0Size, new->PchTraceHubMemReg0Size); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 310: old->PchTraceHubMemReg1Size, new->PchTraceHubMemReg1Size); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 310: old->PchTraceHubMemReg1Size, new->PchTraceHubMemReg1Size); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 323: fsp_display_upd_value("DdrFreqLimit", 2, old->DdrFreqLimit, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 324: new->DdrFreqLimit); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 324: new->DdrFreqLimit); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 325: fsp_display_upd_value("FreqSaGvLow", 2, old->FreqSaGvLow, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 326: new->FreqSaGvLow); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 326: new->FreqSaGvLow); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 327: #if ! CONFIG(SOC_INTEL_COMETLAKE) space prohibited after that '!' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 329: fsp_display_upd_value("FreqSaGvMid", 2, old->FreqSaGvMid, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 330: new->FreqSaGvMid); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 330: new->FreqSaGvMid); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 332: fsp_display_upd_value("RMT", 1, old->RMT, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 333: new->RMT); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 333: new->RMT); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 334: fsp_display_upd_value("DisableDimmChannel0", 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 335: old->DisableDimmChannel0, new->DisableDimmChannel0); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 335: old->DisableDimmChannel0, new->DisableDimmChannel0); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 336: fsp_display_upd_value("DisableDimmChannel1", 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 337: old->DisableDimmChannel1, new->DisableDimmChannel1); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 337: old->DisableDimmChannel1, new->DisableDimmChannel1); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 338: fsp_display_upd_value("ScramblerSupport", 1, old->ScramblerSupport, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 339: new->ScramblerSupport); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 339: new->ScramblerSupport); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 340: fsp_display_upd_value("SkipMpInit", 1, old->SkipMpInit, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 341: new->SkipMpInit); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 341: new->SkipMpInit); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 343: fsp_display_upd_value("SpdProfileSelected", 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 344: old->SpdProfileSelected, new->SpdProfileSelected); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 344: old->SpdProfileSelected, new->SpdProfileSelected); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 345: fsp_display_upd_value("RefClk", 1, old->RefClk, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 346: new->RefClk); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 346: new->RefClk); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 347: fsp_display_upd_value("VddVoltage", 2, old->VddVoltage, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 348: new->VddVoltage); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 348: new->VddVoltage); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 349: fsp_display_upd_value("Ratio", 1, old->Ratio, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 350: new->Ratio); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 350: new->Ratio); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 351: fsp_display_upd_value("OddRatioMode", 1, old->OddRatioMode, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 352: new->OddRatioMode); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 352: new->OddRatioMode); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 353: fsp_display_upd_value("tCL", 1, old->tCL, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 354: new->tCL); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 354: new->tCL); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 355: fsp_display_upd_value("tCWL", 1, old->tCWL, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 356: new->tCWL); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 356: new->tCWL); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 357: fsp_display_upd_value("tRCDtRP", 1, old->tRCDtRP, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 358: new->tRCDtRP); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 358: new->tRCDtRP); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 359: fsp_display_upd_value("tRRD", 1, old->tRRD, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 360: new->tRRD); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 360: new->tRRD); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 361: fsp_display_upd_value("tFAW", 2, old->tFAW, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 362: new->tFAW); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 362: new->tFAW); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 363: fsp_display_upd_value("tRAS", 2, old->tRAS, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 364: new->tRAS); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 364: new->tRAS); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 365: fsp_display_upd_value("tREFI", 2, old->tREFI, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 366: new->tREFI); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 366: new->tREFI); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 367: fsp_display_upd_value("tRFC", 2, old->tRFC, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 368: new->tRFC); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 368: new->tRFC); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 369: fsp_display_upd_value("tRTP", 1, old->tRTP, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 370: new->tRTP); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 370: new->tRTP); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 371: fsp_display_upd_value("tWR", 1, old->tWR, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 372: new->tWR); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 372: new->tWR); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 373: fsp_display_upd_value("NModeSupport", 1, old->NModeSupport, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 374: new->NModeSupport); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 374: new->NModeSupport); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 375: fsp_display_upd_value("DllBwEn0", 1, old->DllBwEn0, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 376: new->DllBwEn0); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 376: new->DllBwEn0); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 377: fsp_display_upd_value("DllBwEn1", 1, old->DllBwEn1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 378: new->DllBwEn1); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 378: new->DllBwEn1); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 379: fsp_display_upd_value("DllBwEn2", 1, old->DllBwEn2, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 380: new->DllBwEn2); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 380: new->DllBwEn2); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 381: fsp_display_upd_value("DllBwEn3", 1, old->DllBwEn3, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 382: new->DllBwEn3); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 382: new->DllBwEn3); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 383: fsp_display_upd_value("IsvtIoPort", 1, old->IsvtIoPort, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 384: new->IsvtIoPort); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 384: new->IsvtIoPort); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 385: fsp_display_upd_value("CpuTraceHubMode", 1, old->CpuTraceHubMode, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 386: new->CpuTraceHubMode); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 386: new->CpuTraceHubMode); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 387: fsp_display_upd_value("CpuTraceHubMemReg0Size", 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 388: old->CpuTraceHubMemReg0Size, new->CpuTraceHubMemReg0Size); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 388: old->CpuTraceHubMemReg0Size, new->CpuTraceHubMemReg0Size); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 389: fsp_display_upd_value("CpuTraceHubMemReg1Size", 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 390: old->CpuTraceHubMemReg1Size, new->CpuTraceHubMemReg1Size); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 390: old->CpuTraceHubMemReg1Size, new->CpuTraceHubMemReg1Size); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 391: fsp_display_upd_value("PeciC10Reset", 1, old->PeciC10Reset, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 392: new->PeciC10Reset); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 392: new->PeciC10Reset); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 393: fsp_display_upd_value("PeciSxReset", 1, old->PeciSxReset, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 394: new->PeciSxReset); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 394: new->PeciSxReset); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 396: fsp_display_upd_value("PchHdaEnable", 1, old->PchHdaEnable, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 397: new->PchHdaEnable); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 397: new->PchHdaEnable); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 398: fsp_display_upd_value("PchIshEnable", 1, old->PchIshEnable, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 399: new->PchIshEnable); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 399: new->PchIshEnable); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 400: fsp_display_upd_value("HeciTimeouts", 1, old->HeciTimeouts, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 401: new->HeciTimeouts); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 401: new->HeciTimeouts); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 403: fsp_display_upd_value("Heci1BarAddress", 4, old->Heci1BarAddress, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 404: new->Heci1BarAddress); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 404: new->Heci1BarAddress); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 405: fsp_display_upd_value("Heci2BarAddress", 4, old->Heci2BarAddress, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 406: new->Heci2BarAddress); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 406: new->Heci2BarAddress); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 407: fsp_display_upd_value("Heci3BarAddress", 4, old->Heci3BarAddress, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 408: new->Heci3BarAddress); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 408: new->Heci3BarAddress); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 409: fsp_display_upd_value("SgDelayAfterPwrEn", 2, old->SgDelayAfterPwrEn, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 410: new->SgDelayAfterPwrEn); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 410: new->SgDelayAfterPwrEn); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 411: fsp_display_upd_value("SgDelayAfterHoldReset", 2, old->SgDelayAfterHoldReset, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 412: new->SgDelayAfterHoldReset); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 412: new->SgDelayAfterHoldReset); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 413: fsp_display_upd_value("MmioSizeAdjustment", 2, old->MmioSizeAdjustment, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 414: new->MmioSizeAdjustment); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 414: new->MmioSizeAdjustment); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 415: fsp_display_upd_value("DmiGen3ProgramStaticEq", 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 416: old->DmiGen3ProgramStaticEq, new->DmiGen3ProgramStaticEq); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 416: old->DmiGen3ProgramStaticEq, new->DmiGen3ProgramStaticEq); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 417: fsp_display_upd_value("Peg0Enable", 1, old->Peg0Enable, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 418: new->Peg0Enable); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 418: new->Peg0Enable); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 419: fsp_display_upd_value("Peg1Enable", 1, old->Peg1Enable, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 420: new->Peg1Enable); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 420: new->Peg1Enable); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 421: fsp_display_upd_value("Peg2Enable", 1, old->Peg2Enable, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 422: new->Peg2Enable); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 422: new->Peg2Enable); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 423: fsp_display_upd_value("Peg3Enable", 1, old->Peg3Enable, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 424: new->Peg3Enable); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 424: new->Peg3Enable); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 425: fsp_display_upd_value("Peg0MaxLinkSpeed", 1, old->Peg0MaxLinkSpeed, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 426: new->Peg0MaxLinkSpeed); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 426: new->Peg0MaxLinkSpeed); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 427: fsp_display_upd_value("Peg1MaxLinkSpeed", 1, old->Peg1MaxLinkSpeed, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 428: new->Peg1MaxLinkSpeed); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 428: new->Peg1MaxLinkSpeed); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 429: fsp_display_upd_value("Peg2MaxLinkSpeed", 1, old->Peg2MaxLinkSpeed, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 430: new->Peg2MaxLinkSpeed); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 430: new->Peg2MaxLinkSpeed); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 431: fsp_display_upd_value("Peg3MaxLinkSpeed", 1, old->Peg3MaxLinkSpeed, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 432: new->Peg3MaxLinkSpeed); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 432: new->Peg3MaxLinkSpeed); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 433: fsp_display_upd_value("Peg0MaxLinkWidth", 1, old->Peg0MaxLinkWidth, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 434: new->Peg0MaxLinkWidth); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 434: new->Peg0MaxLinkWidth); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 435: fsp_display_upd_value("Peg1MaxLinkWidth", 1, old->Peg1MaxLinkWidth, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 436: new->Peg1MaxLinkWidth); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 436: new->Peg1MaxLinkWidth); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 437: fsp_display_upd_value("Peg2MaxLinkWidth", 1, old->Peg2MaxLinkWidth, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 438: new->Peg2MaxLinkWidth); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 438: new->Peg2MaxLinkWidth); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 439: fsp_display_upd_value("Peg3MaxLinkWidth", 1, old->Peg3MaxLinkWidth, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 440: new->Peg3MaxLinkWidth); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 440: new->Peg3MaxLinkWidth); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 441: fsp_display_upd_value("Peg0PowerDownUnusedLanes", 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 442: old->Peg0PowerDownUnusedLanes, new->Peg0PowerDownUnusedLanes); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 442: old->Peg0PowerDownUnusedLanes, new->Peg0PowerDownUnusedLanes); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 443: fsp_display_upd_value("Peg1PowerDownUnusedLanes", 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 444: old->Peg1PowerDownUnusedLanes, new->Peg1PowerDownUnusedLanes); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 444: old->Peg1PowerDownUnusedLanes, new->Peg1PowerDownUnusedLanes); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 445: fsp_display_upd_value("Peg2PowerDownUnusedLanes", 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 446: old->Peg2PowerDownUnusedLanes, new->Peg2PowerDownUnusedLanes); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 446: old->Peg2PowerDownUnusedLanes, new->Peg2PowerDownUnusedLanes); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 447: fsp_display_upd_value("Peg3PowerDownUnusedLanes", 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 448: old->Peg3PowerDownUnusedLanes, new->Peg3PowerDownUnusedLanes); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 448: old->Peg3PowerDownUnusedLanes, new->Peg3PowerDownUnusedLanes); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 449: fsp_display_upd_value("InitPcieAspmAfterOprom", 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 450: old->InitPcieAspmAfterOprom, new->InitPcieAspmAfterOprom); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 450: old->InitPcieAspmAfterOprom, new->InitPcieAspmAfterOprom); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 451: fsp_display_upd_value("PegDisableSpreadSpectrumClocking", 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 452: old->PegDisableSpreadSpectrumClocking, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 452: old->PegDisableSpreadSpectrumClocking, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 453: new->PegDisableSpreadSpectrumClocking); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35802/1/src/soc/intel/cannonlake/ro... PS1, Line 453: new->PegDisableSpreadSpectrumClocking); please, no spaces at the start of a line
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35802
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Add debugging of a number of FSPM parameters ......................................................................
soc/intel/cannonlake: Add debugging of a number of FSPM parameters
This implements soc_display_fspm_upd_params for soc/intel/cannonlake
Some parameters are available only on Coffee Lake FSP or Comet Lake FSP
Tested on System76 galp3-c (Coffee Lake FSP) and System76 galp4 (Comet Lake FSP)
Change-Id: I01c7a07ce7446ff762849c64600e728339a4974f Signed-Of-By: Jeremy Soller jeremy@system76.com --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 313 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35802/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35802 )
Change subject: soc/intel/cannonlake: Add debugging of a number of FSPM parameters ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35802/2/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/35802/2/src/soc/intel/cannonlake/ro... PS2, Line 327: #if ! CONFIG(SOC_INTEL_COMETLAKE) space prohibited after that '!' (ctx:WxW)
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35802
to look at the new patch set (#3).
Change subject: soc/intel/cannonlake: Add debugging of a number of FSPM parameters ......................................................................
soc/intel/cannonlake: Add debugging of a number of FSPM parameters
This implements soc_display_fspm_upd_params for soc/intel/cannonlake
Some parameters are available only on Coffee Lake FSP or Comet Lake FSP
Tested on System76 galp3-c (Coffee Lake FSP) and System76 galp4 (Comet Lake FSP)
Change-Id: I01c7a07ce7446ff762849c64600e728339a4974f Signed-off-by: Jeremy Soller jeremy@system76.com --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 313 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35802/3
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35802
to look at the new patch set (#4).
Change subject: soc/intel/cannonlake: Add debugging of a number of FSPM parameters ......................................................................
soc/intel/cannonlake: Add debugging of a number of FSPM parameters
This implements soc_display_fspm_upd_params for soc/intel/cannonlake
Some parameters are available only on Coffee Lake FSP or Comet Lake FSP
Tested on System76 galp3-c (Coffee Lake FSP) and System76 galp4 (Comet Lake FSP)
Change-Id: I01c7a07ce7446ff762849c64600e728339a4974f Signed-off-by: Jeremy Soller jeremy@system76.com --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 313 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35802/4
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35802 )
Change subject: soc/intel/cannonlake: Add debugging of a number of FSPM parameters ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35802/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35802/4//COMMIT_MSG@9 PS4, Line 9: This implements soc_display_fspm_upd_params for soc/intel/cannonlake Please add a dot/period at the end of sentences.
https://review.coreboot.org/c/coreboot/+/35802/4//COMMIT_MSG@15 PS4, Line 15: How much do these string increase the image size?
https://review.coreboot.org/c/coreboot/+/35802/4/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/35802/4/src/soc/intel/cannonlake/ro... PS4, Line 146: const FSPM_UPD *fspm_new_upd) Fits into 96 characters.
https://review.coreboot.org/c/coreboot/+/35802/4/src/soc/intel/cannonlake/ro... PS4, Line 155: printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); There is a Kconfig value for debugging RAM init, I believe.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35802 )
Change subject: soc/intel/cannonlake: Add debugging of a number of FSPM parameters ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35802/4/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/35802/4/src/soc/intel/cannonlake/ro... PS4, Line 155: printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
There is a Kconfig value for debugging RAM init, I believe.
Except that this is not raminit debugging. I think there's a Kconfig option for displaying FSP UPDs though
Jeremy Soller has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35802 )
Change subject: soc/intel/cannonlake: Add debugging of a number of FSPM parameters ......................................................................
Abandoned
I'm no longer using this change, as it has been difficult to keep it up to date with upstream changes
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
-
Jeremy Soller (Code Review)
-
Paul Menzel (Code Review)