[S] Change in coreboot[master]: mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low

[Sukumar Ghorai (Code Review)]

Attention is currently required from: Subrata Banik, Kapil Porwal, Ivy Jian, Eric Lai, Utkarsh H Patel.

Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70196 )

Change subject: mb/google/rex: Cnfigure `SLP_S0_GATE_R` aka GPP_H14 PIN low
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Patch Set 3:

(1 comment)

Patchset:

PS3:
> > I think we should wait Intel verify this, weird. […]

PAD_CFG_GPO(GPP_H14, 0, PLTRST), -> this does not solve the problem.
We have tested with comment the line //PAD_CFG_GPO(GPP_H14, 0, PLTRST),

a) It must need to be high 
b) And need the DSDT method to enable/disable SLP_S0_GATE_R at runtime; As in brya https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+...