Patch set updated for coreboot: Add makefile for Saddle Brook platform and also gpio config for Skylake-H sku
Martin Roth (martinroth@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16609 -gerrit commit b143e5dfa4dc8fb8ab5488382be1d7a6de4f0586 Author: Teo Boon Tiong <boon.tiong.teo@intel.com> Date: Thu Sep 15 12:36:03 2016 +0800 Add makefile for Saddle Brook platform and also gpio config for Skylake-H sku Change-Id: I384a98990d3b4ffd1e32b272e7a681e1c117c298 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> --- src/mainboard/intel/sklsdlbrk/Makefile.inc | 24 + src/mainboard/intel/sklsdlbrk/board_info.txt | 2 + src/mainboard/intel/sklsdlbrk/chromeos.c | 70 +++ src/mainboard/intel/sklsdlbrk/gpio.h | 276 +++++++++++ src/mainboard/intel/sklsdlbrk/mainboard.c | 104 ++++ src/mainboard/intel/sklsdlbrk/pei_data.c | 56 +++ src/mainboard/intel/sklsdlbrk/ramstage.c | 24 + src/soc/intel/skylake/acpi/gpio.asl | 21 + src/soc/intel/skylake/gpio.c | 13 + src/soc/intel/skylake/include/fsp11/soc/romstage.h | 1 - src/soc/intel/skylake/include/soc/gpio_defs.h | 539 ++++++++++++++++++++- src/soc/intel/skylake/include/soc/pei_data.h | 2 + 12 files changed, 1130 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/sklsdlbrk/Makefile.inc b/src/mainboard/intel/sklsdlbrk/Makefile.inc new file mode 100644 index 0000000..cdeb1b6 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +romstage-y += pei_data.c + +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +ramstage-y += pei_data.c +ramstage-y += ramstage.c diff --git a/src/mainboard/intel/sklsdlbrk/board_info.txt b/src/mainboard/intel/sklsdlbrk/board_info.txt new file mode 100644 index 0000000..15ddb1f --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/board_info.txt @@ -0,0 +1,2 @@ +Category: eval +Release year: 2015 diff --git a/src/mainboard/intel/sklsdlbrk/chromeos.c b/src/mainboard/intel/sklsdlbrk/chromeos.c new file mode 100644 index 0000000..821b8b8 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/chromeos.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <rules.h> +#include <soc/gpio.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", + get_recovery_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", + get_lid_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); +} +#endif /* ENV_RAMSTAGE */ + +int get_lid_switch(void) +{ + /* Default to force open */ + return 1; +} + +/* The dev-switch is virtual */ +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/mainboard/intel/sklsdlbrk/gpio.h b/src/mainboard/intel/sklsdlbrk/gpio.h new file mode 100644 index 0000000..4109f6b --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/gpio.h @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ +#define GPE_WLAN_WAKE GPE0_DW0_16 + +/* Input device interrupt configuration */ +#define TOUCHPAD_INT_L GPP_B3_IRQ +#define TOUCHSCREEN_INT_L GPP_E7_IRQ +#define MIC_INT_L GPP_F10_IRQ + +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ +#define EC_SCI_GPI GPE0_DW2_16 +#define EC_SMI_GPI GPP_E15 + +#ifndef __ACPI__ +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA# */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +/* EC_HID_INT */ PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), +/* ISH_KB_PROX_INT */ PAD_CFG_GPI(GPP_A12, NONE, DEEP), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SD_1P8_SEL */ +/* SD_PWR_EN */ +/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), +/* ISH_GP1 */ /* GPP_A19 */ +/* GYRO_DRDY */ +/* FLIP_ACCEL_INT */ +/* GYRO_INT */ +/* ISH_GP5 */ /* GPP_A23 */ + +/* CORE_VID0 */ /* GPP_B0 */ +/* CORE_VID1 */ /* GPP_B1 */ +/* HSJ_MIC_DET */ +/* TRACKPAD_INT */ PAD_CFG_GPO(GPP_B3, 1, DEEP), +/* BT_RF_KILL */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1), +/* SRCCLKREQ0# */ /* GPP_B5 */ +/* WIFI_CLK_REQ */ +/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* SRCCLKREQ3# */ /* GPP_B8 */ +/* SSD_CLK_REQ */ +/* SRCCLKREQ5# */ /* GPP_B10 */ +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1), +/* GSPI0_CS# */ /* GPP_B15 */ +/* WLAN_PCIE_WAKE */ +/* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP), +/* GSPI0_MOSI */ /* GPP_B18 */ +/* CCODEC_SPI_CS */ +/* CODEC_SPI_CLK */ +/* CODEC_SPI_MISO */ +/* CODEC_SPI_MOSI */ +/* SM1ALERT# */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF1), + +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_NF(GPP_C2, 20K_PD, DEEP, NF1), +/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0ALERT# */ /* GPP_C5 */ +/* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* USB_CTL */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* UART0_RXD */ /* GPP_C8 */ +/* UART0_TXD */ /* GPP_C9 */ +/* NFC_RST* */ +/* EN_PP3300_KEPLER */ +/* PCH_MEM_CFG0 */ +/* PCH_MEM_CFG1 */ +/* PCH_MEM_CFG2 */ +/* PCH_MEM_CFG3 */ +/* I2C0_SDA */ +/* I2C0_SCL */ +/* I2C1_SDA */ +/* I2C1_SCL */ +/* GD_UART2_RXD */ +/* GD_UART2_TXD */ +/* TCH_PNL_PWREN */ +/* SPI_WP_STATUS */ + +/* ITCH_SPI_CS */ /* GPP_D0 */ +/* ITCH_SPI_CLK */ /* GPP_D1 */ +/* ITCH_SPI_MISO_1 */ /* GPP_D2 */ +/* ITCH_SPI_MISO_0 */ /* GPP_D3 */ +/* CAM_FLASH_STROBE */ +/* EN_PP3300_DX_EMMC */ +/* EN_PP1800_DX_EMMC */ +/* SH_I2C1_SDA */ +/* SH_I2C1_SCL */ +/* TBD */ +/* USB_A0_ILIM_SEL */ +/* USB_A1_ILIM_SEL */ +/* EN_PP3300_DX_CAM */ +/* EN_PP1800_DX_AUDIO */ +/* ISH_UART0_TXD */ /* GPP_D14 */ +/* ISH_UART0_RTS */ /* GPP_D15 */ +/* ISH_UART0_CTS */ /* GPP_D16 */ +/* DMIC_CLK_1 */ +/* DMIC_DATA_1 */ +/* DMIC_CLK_0 */ +/* DMIC_DATA_0 */ +/* ITCH_SPI_D2 */ /* GPP_D21 */ +/* ITCH_SPI_D3 */ /* GPP_D22 */ +/* I2S_MCLK */ + +/* SPI_TPM_IRQ */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), +/* SATAXPCIE1 */ /* GPP_E1 */ +/* SSD_PEDET */ +/* CPU_GP0 */ +/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* SATA_DEVSLP1 */ /* GPP_E5 */ +/* SATA_DEVSLP2 */ /* GPP_E6 */ +/* TCH_PNL_INTR* */ +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + +/* I2S2_SCLK */ +/* I2S2_SFRM */ +/* I2S2_TXD */ PAD_CFG_GPO(GPP_F2, 0, DEEP), +/* I2S2_RXD */ +/* I2C2_SDA */ /* GPP_F4 */ +/* I2C2_SCL */ /* GPP_F5 */ +/* I2C3_SDA */ /* GPP_F6 */ +/* I2C3_SCL */ /* GPP_F7 */ +/* I2C4_SDA */ +/* I2C4_SDA */ +/* AUDIO_IRQ */ +/* I2C5_SCL */ /* GPP_F11 */ +/* EMMC_CMD */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_GPO(GPP_F17, 1, DEEP), +/* EMMC_DATA5 */ PAD_CFG_GPO(GPP_F18, 1, DEEP), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_GPO(GPP_F22, 1, DEEP), + /* GPP_F23 */ + +/* SD_CMD */ /* GPP_G0 */ +/* SD_DATA0 */ +/* SD_DATA1 */ +/* SD_DATA2 */ +/* SD_DATA3 */ +/* SD_CD# */ +/* SD_CLK */ +/* SD_WP */ +/* TBD */ PAD_CFG_GPO(GPP_G8, 1, DEEP), +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ PAD_CFG_GPI(GPP_G23, NONE, DEEP), + +/* SD_CMD */ /* GPP_H0 */ +/* SD_DATA0 */ +/* SD_DATA1 */ +/* SD_DATA2 */ +/* SD_DATA3 */ +/* SD_CD# */ +/* SD_CLK */ +/* SD_WP */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ +/* TBD */ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), +/* TBD */ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), +/* TBD */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), +/* TBD */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), +/* TBD */ + +/* SD_CMD */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + +/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7 */ +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ +}; + +#endif + +#endif diff --git a/src/mainboard/intel/sklsdlbrk/mainboard.c b/src/mainboard/intel/sklsdlbrk/mainboard.c new file mode 100644 index 0000000..91a89a9 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/mainboard.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#include <arch/interrupt.h> +#endif + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ + int res = 0; + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Grahpics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit 1 or bit 2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) * + * bit 2 = EFP * + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) * + * bit 6 = EFP2 * + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f40: + /* + * Hook to select boot panel type + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f51: + /* + * Hook to select Active LFP Configuration + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + default: + printk(BIOS_DEBUG, "Unknown INT16 function %04x!\n", X86_AX); + break; + } + return res; + +} +#endif + +static void mainboard_init(device_t dev) +{ +#if CONFIG_VGA_ROM_RUN + printk(BIOS_DEBUG, "mainboard_init\n"); + /* Install custom int15 handler for VGA oprom */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + +} + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses() +*/ +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/sklsdlbrk/pei_data.c b/src/mainboard/intel/sklsdlbrk/pei_data.c new file mode 100644 index 0000000..5052cd3 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/pei_data.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + + /* DQ byte map for sklrvp board */ + const u8 dq_map[2][12] = { + {0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00}, + {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00} }; + /* DQS CPU<>DRAM map for sklrvp board */ + const u8 dqs_map[2][8] = { + {0, 1, 3, 2, 4, 5, 6, 7}, + {1, 0, 4, 5, 2, 3, 6, 7} }; + + /* Rcomp resistor*/ + const u16 RcompResistor[3] = {121, 81, 100}; + + /* Rcomp target*/ + const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + + pei_data->ec_present = 1; + + pei_data->spd_addresses[0] = 0xA0; + pei_data->spd_addresses[1] = 0x0; + pei_data->spd_addresses[2] = 0xA4; + pei_data->spd_addresses[3] = 0x0; + + memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); + memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); + memcpy(pei_data->RcompResistor, RcompResistor, + sizeof(RcompResistor)); + memcpy(pei_data->RcompTarget, RcompTarget, + sizeof(RcompTarget)); +} diff --git a/src/mainboard/intel/sklsdlbrk/ramstage.c b/src/mainboard/intel/sklsdlbrk/ramstage.c new file mode 100644 index 0000000..563c715 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/ramstage.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index c9116d0..3f57a45 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -75,6 +75,26 @@ Device (GPIO) */ Method (GADD, 1, NotSerialized) { +#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) + /* GPIO Community 0 */ + If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) + { + Store (PID_GPIOCOM0, Local0) + Subtract (Arg0, GPP_A0, Local1) + } + /* GPIO Community 1 */ + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_H23))) + { + Store (PID_GPIOCOM1, Local0) + Subtract (Arg0, GPP_C0, Local1) + } + /* GPIO Community 03*/ + If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_I10))) + { + Store (PID_GPIOCOM3, Local0) + Subtract (Arg0, GPP_I0, Local1) + } +#else /* GPIO Community 0 */ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) { @@ -93,6 +113,7 @@ Method (GADD, 1, NotSerialized) Store (PID_GPIOCOM3, Local0) Subtract (Arg0, GPP_F0, Local1) } +#endif Store (PCRB (Local0), Local2) Add (Local2, PAD_CFG_DW_OFFSET, Local2) Return (Add (Local2, Multiply (Local1, 8))) diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 5b9babf..03eba5b 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -45,12 +45,21 @@ static const struct gpio_community communities[] = { { .port_id = PID_GPIOCOM1, .min = GPP_C0, +#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) + .max = GPP_H23, +#else .max = GPP_E23, +#endif }, { .port_id = PID_GPIOCOM3, +#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) + .min = GPP_I0, + .max = GPP_I10, +#else .min = GPP_F0, .max = GPP_G7, +#endif }, { .port_id = PID_GPIOCOM2, @@ -67,6 +76,10 @@ static const char *gpio_group_names[GPIO_NUM_GROUPS] = { "GPP_E", "GPP_F", "GPP_G", +#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) + "GPP_H", + "GPP_I", +#endif "GPD", }; diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h index 6c40bd6..2d3a198 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h @@ -22,7 +22,6 @@ void systemagent_early_init(void); void intel_early_me_status(void); void enable_smbus(void); -int smbus_read_byte(unsigned device, unsigned address); int early_spi_read_wpsr(u8 *sr); void mainboard_fill_spd_data(struct pei_data *pei_data); diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 112db63..d0391be 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -16,6 +16,543 @@ #ifndef _SOC_GPIO_DEFS_H_ #define _SOC_GPIO_DEFS_H_ +#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +/* + * There are 10 GPIO groups. GPP_A -> GPP_I and GPD. GPD is the special case + * where that group is not so generic. So most of the fixed numbers and macros + * are based on the GPP groups. The GPIO groups are accessed through register + * blocks called communities. + */ +#define GPP_A 0 +#define GPP_B 1 +#define GPP_C 2 +#define GPP_D 3 +#define GPP_E 4 +#define GPP_F 5 +#define GPP_G 6 +#define GPP_H 7 +#define GPP_I 8 +#define GPD 9 +#define GPIO_NUM_GROUPS 10 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group A */ +#define GPP_A0 0 +#define GPP_A1 1 +#define GPP_A2 2 +#define GPP_A3 3 +#define GPP_A4 4 +#define GPP_A5 5 +#define GPP_A6 6 +#define GPP_A7 7 +#define GPP_A8 8 +#define GPP_A9 9 +#define GPP_A10 10 +#define GPP_A11 11 +#define GPP_A12 12 +#define GPP_A13 13 +#define GPP_A14 14 +#define GPP_A15 15 +#define GPP_A16 16 +#define GPP_A17 17 +#define GPP_A18 18 +#define GPP_A19 19 +#define GPP_A20 20 +#define GPP_A21 21 +#define GPP_A22 22 +#define GPP_A23 23 +/* Group B */ +#define GPP_B0 24 +#define GPP_B1 25 +#define GPP_B2 26 +#define GPP_B3 27 +#define GPP_B4 28 +#define GPP_B5 29 +#define GPP_B6 30 +#define GPP_B7 31 +#define GPP_B8 32 +#define GPP_B9 33 +#define GPP_B10 34 +#define GPP_B11 35 +#define GPP_B12 36 +#define GPP_B13 37 +#define GPP_B14 38 +#define GPP_B15 39 +#define GPP_B16 40 +#define GPP_B17 41 +#define GPP_B18 42 +#define GPP_B19 43 +#define GPP_B20 44 +#define GPP_B21 45 +#define GPP_B22 46 +#define GPP_B23 47 +/* Group C */ +#define GPP_C0 48 +#define GPP_C1 49 +#define GPP_C2 50 +#define GPP_C3 51 +#define GPP_C4 52 +#define GPP_C5 53 +#define GPP_C6 54 +#define GPP_C7 55 +#define GPP_C8 56 +#define GPP_C9 57 +#define GPP_C10 58 +#define GPP_C11 59 +#define GPP_C12 60 +#define GPP_C13 61 +#define GPP_C14 62 +#define GPP_C15 63 +#define GPP_C16 64 +#define GPP_C17 65 +#define GPP_C18 66 +#define GPP_C19 67 +#define GPP_C20 68 +#define GPP_C21 69 +#define GPP_C22 70 +#define GPP_C23 71 +/* Group D */ +#define GPP_D0 72 +#define GPP_D1 73 +#define GPP_D2 74 +#define GPP_D3 75 +#define GPP_D4 76 +#define GPP_D5 77 +#define GPP_D6 78 +#define GPP_D7 79 +#define GPP_D8 80 +#define GPP_D9 81 +#define GPP_D10 82 +#define GPP_D11 83 +#define GPP_D12 84 +#define GPP_D13 85 +#define GPP_D14 86 +#define GPP_D15 87 +#define GPP_D16 88 +#define GPP_D17 89 +#define GPP_D18 90 +#define GPP_D19 91 +#define GPP_D20 92 +#define GPP_D21 93 +#define GPP_D22 94 +#define GPP_D23 95 +/* Group E */ +#define GPP_E0 96 +#define GPP_E1 97 +#define GPP_E2 98 +#define GPP_E3 99 +#define GPP_E4 100 +#define GPP_E5 101 +#define GPP_E6 102 +#define GPP_E7 103 +#define GPP_E8 104 +#define GPP_E9 105 +#define GPP_E10 106 +#define GPP_E11 107 +#define GPP_E12 108 +/* Group F */ +#define GPP_F0 109 +#define GPP_F1 110 +#define GPP_F2 111 +#define GPP_F3 112 +#define GPP_F4 113 +#define GPP_F5 114 +#define GPP_F6 115 +#define GPP_F7 116 +#define GPP_F8 117 +#define GPP_F9 118 +#define GPP_F10 119 +#define GPP_F11 120 +#define GPP_F12 121 +#define GPP_F13 122 +#define GPP_F14 123 +#define GPP_F15 124 +#define GPP_F16 125 +#define GPP_F17 126 +#define GPP_F18 127 +#define GPP_F19 128 +#define GPP_F20 129 +#define GPP_F21 130 +#define GPP_F22 131 +#define GPP_F23 132 +/* Group G */ +#define GPP_G0 133 +#define GPP_G1 134 +#define GPP_G2 135 +#define GPP_G3 136 +#define GPP_G4 137 +#define GPP_G5 138 +#define GPP_G6 139 +#define GPP_G7 140 +#define GPP_G8 141 +#define GPP_G9 142 +#define GPP_G10 143 +#define GPP_G11 144 +#define GPP_G12 145 +#define GPP_G13 146 +#define GPP_G14 147 +#define GPP_G15 148 +#define GPP_G16 149 +#define GPP_G17 150 +#define GPP_G18 151 +#define GPP_G19 152 +#define GPP_G20 153 +#define GPP_G21 154 +#define GPP_G22 155 +#define GPP_G23 156 +/* Group H */ +#define GPP_H0 157 +#define GPP_H1 158 +#define GPP_H2 159 +#define GPP_H3 160 +#define GPP_H4 161 +#define GPP_H5 162 +#define GPP_H6 163 +#define GPP_H7 164 +#define GPP_H8 165 +#define GPP_H9 166 +#define GPP_H10 167 +#define GPP_H11 168 +#define GPP_H12 169 +#define GPP_H13 170 +#define GPP_H14 171 +#define GPP_H15 172 +#define GPP_H16 173 +#define GPP_H17 174 +#define GPP_H18 175 +#define GPP_H19 176 +#define GPP_H20 177 +#define GPP_H21 178 +#define GPP_H22 179 +#define GPP_H23 180 +/* Group I */ +#define GPP_I0 181 +#define GPP_I1 182 +#define GPP_I2 183 +#define GPP_I3 184 +#define GPP_I4 185 +#define GPP_I5 186 +#define GPP_I6 187 +#define GPP_I7 188 +#define GPP_I8 189 +#define GPP_I9 190 +#define GPP_I10 191 +/* Group GPD */ +#define GPD0 192 +#define GPD1 193 +#define GPD2 194 +#define GPD3 195 +#define GPD4 196 +#define GPD5 197 +#define GPD6 198 +#define GPD7 199 +#define GPD8 200 +#define GPD9 201 +#define GPD10 202 +#define GPD11 203 + +/* hj88: FIXME */ +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group A */ +#define GPP_A0_IRQ 0x18 +#define GPP_A1_IRQ 0x19 +#define GPP_A2_IRQ 0x1a +#define GPP_A3_IRQ 0x1b +#define GPP_A4_IRQ 0x1c +#define GPP_A5_IRQ 0x1d +#define GPP_A6_IRQ 0x1e +#define GPP_A7_IRQ 0x1f +#define GPP_A8_IRQ 0x20 +#define GPP_A9_IRQ 0x21 +#define GPP_A10_IRQ 0x22 +#define GPP_A11_IRQ 0x23 +#define GPP_A12_IRQ 0x24 +#define GPP_A13_IRQ 0x25 +#define GPP_A14_IRQ 0x26 +#define GPP_A15_IRQ 0x27 +#define GPP_A16_IRQ 0x28 +#define GPP_A17_IRQ 0x29 +#define GPP_A18_IRQ 0x2a +#define GPP_A19_IRQ 0x2b +#define GPP_A20_IRQ 0x2c +#define GPP_A21_IRQ 0x2d +#define GPP_A22_IRQ 0x2e +#define GPP_A23_IRQ 0x2f +/* Group B */ +#define GPP_B0_IRQ 0x30 +#define GPP_B1_IRQ 0x31 +#define GPP_B2_IRQ 0x32 +#define GPP_B3_IRQ 0x33 +#define GPP_B4_IRQ 0x34 +#define GPP_B5_IRQ 0x35 +#define GPP_B6_IRQ 0x36 +#define GPP_B7_IRQ 0x37 +#define GPP_B8_IRQ 0x38 +#define GPP_B9_IRQ 0x39 +#define GPP_B10_IRQ 0x3a +#define GPP_B11_IRQ 0x3b +#define GPP_B12_IRQ 0x3c +#define GPP_B13_IRQ 0x3d +#define GPP_B14_IRQ 0x3e +#define GPP_B15_IRQ 0x3f +#define GPP_B16_IRQ 0x40 +#define GPP_B17_IRQ 0x41 +#define GPP_B18_IRQ 0x42 +#define GPP_B19_IRQ 0x43 +#define GPP_B20_IRQ 0x44 +#define GPP_B21_IRQ 0x45 +#define GPP_B22_IRQ 0x46 +#define GPP_B23_IRQ 0x47 +/* Group C */ +#define GPP_C0_IRQ 0x48 +#define GPP_C1_IRQ 0x49 +#define GPP_C2_IRQ 0x4a +#define GPP_C3_IRQ 0x4b +#define GPP_C4_IRQ 0x4c +#define GPP_C5_IRQ 0x4d +#define GPP_C6_IRQ 0x4e +#define GPP_C7_IRQ 0x4f +#define GPP_C8_IRQ 0x50 +#define GPP_C9_IRQ 0x51 +#define GPP_C10_IRQ 0x52 +#define GPP_C11_IRQ 0x53 +#define GPP_C12_IRQ 0x54 +#define GPP_C13_IRQ 0x55 +#define GPP_C14_IRQ 0x56 +#define GPP_C15_IRQ 0x57 +#define GPP_C16_IRQ 0x58 +#define GPP_C17_IRQ 0x59 +#define GPP_C18_IRQ 0x5a +#define GPP_C19_IRQ 0x5b +#define GPP_C20_IRQ 0x5c +#define GPP_C21_IRQ 0x5d +#define GPP_C22_IRQ 0x5e +#define GPP_C23_IRQ 0x5f +/* Group D */ +#define GPP_D0_IRQ 0x60 +#define GPP_D1_IRQ 0x61 +#define GPP_D2_IRQ 0x62 +#define GPP_D3_IRQ 0x63 +#define GPP_D4_IRQ 0x64 +#define GPP_D5_IRQ 0x65 +#define GPP_D6_IRQ 0x66 +#define GPP_D7_IRQ 0x67 +#define GPP_D8_IRQ 0x68 +#define GPP_D9_IRQ 0x69 +#define GPP_D10_IRQ 0x6a +#define GPP_D11_IRQ 0x6b +#define GPP_D12_IRQ 0x6c +#define GPP_D13_IRQ 0x6d +#define GPP_D14_IRQ 0x6e +#define GPP_D15_IRQ 0x6f +#define GPP_D16_IRQ 0x70 +#define GPP_D17_IRQ 0x71 +#define GPP_D18_IRQ 0x72 +#define GPP_D19_IRQ 0x73 +#define GPP_D20_IRQ 0x74 +#define GPP_D21_IRQ 0x75 +#define GPP_D22_IRQ 0x76 +#define GPP_D23_IRQ 0x77 +/* Group E */ +#define GPP_E0_IRQ 0x18 +#define GPP_E1_IRQ 0x19 +#define GPP_E2_IRQ 0x1a +#define GPP_E3_IRQ 0x1b +#define GPP_E4_IRQ 0x1c +#define GPP_E5_IRQ 0x1d +#define GPP_E6_IRQ 0x1e +#define GPP_E7_IRQ 0x1f +#define GPP_E8_IRQ 0x20 +#define GPP_E9_IRQ 0x21 +#define GPP_E10_IRQ 0x22 +#define GPP_E11_IRQ 0x23 +#define GPP_E12_IRQ 0x24 +#define GPP_E13_IRQ 0x25 +#define GPP_E14_IRQ 0x26 +#define GPP_E15_IRQ 0x27 +#define GPP_E16_IRQ 0x28 +#define GPP_E17_IRQ 0x29 +#define GPP_E18_IRQ 0x2a +#define GPP_E19_IRQ 0x2b +#define GPP_E20_IRQ 0x2c +#define GPP_E21_IRQ 0x2d +#define GPP_E22_IRQ 0x2e +#define GPP_E23_IRQ 0x2f +/* Group F */ +#define GPP_F0_IRQ 0x30 +#define GPP_F1_IRQ 0x31 +#define GPP_F2_IRQ 0x32 +#define GPP_F3_IRQ 0x33 +#define GPP_F4_IRQ 0x34 +#define GPP_F5_IRQ 0x35 +#define GPP_F6_IRQ 0x36 +#define GPP_F7_IRQ 0x37 +#define GPP_F8_IRQ 0x38 +#define GPP_F9_IRQ 0x39 +#define GPP_F10_IRQ 0x3a +#define GPP_F11_IRQ 0x3b +#define GPP_F12_IRQ 0x3c +#define GPP_F13_IRQ 0x3d +#define GPP_F14_IRQ 0x3e +#define GPP_F15_IRQ 0x3f +#define GPP_F16_IRQ 0x40 +#define GPP_F17_IRQ 0x41 +#define GPP_F18_IRQ 0x42 +#define GPP_F19_IRQ 0x43 +#define GPP_F20_IRQ 0x44 +#define GPP_F21_IRQ 0x45 +#define GPP_F22_IRQ 0x46 +#define GPP_F23_IRQ 0x47 +/* Group G */ +#define GPP_G0_IRQ 0x48 +#define GPP_G1_IRQ 0x49 +#define GPP_G2_IRQ 0x4a +#define GPP_G3_IRQ 0x4b +#define GPP_G4_IRQ 0x4c +#define GPP_G5_IRQ 0x4d +#define GPP_G6_IRQ 0x4e +#define GPP_G7_IRQ 0x4f +/* Group GPD */ +#define GPD0_IRQ 0x50 +#define GPD1_IRQ 0x51 +#define GPD2_IRQ 0x52 +#define GPD3_IRQ 0x53 +#define GPD4_IRQ 0x54 +#define GPD5_IRQ 0x55 +#define GPD6_IRQ 0x56 +#define GPD7_IRQ 0x57 +#define GPD8_IRQ 0x58 +#define GPD9_IRQ 0x59 +#define GPD10_IRQ 0x5a +#define GPD11_IRQ 0x5b + +/* Register defines. */ +#define MISCCFG_OFFSET 0x10 +#define GPIO_DRIVER_IRQ_ROUTE_MASK 8 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define PAD_OWN_REG_OFFSET 0x20 +#define PAD_OWN_PADS_PER 8 +#define PAD_OWN_WIDTH_PER 4 +#define PAD_OWN_MASK 0x03 +#define PAD_OWN_HOST 0x00 +#define PAD_OWN_ME 0x01 +#define PAD_OWN_ISH 0x02 +#define HOSTSW_OWN_REG_OFFSET 0xd0 +#define HOSTSW_OWN_PADS_PER 24 +#define HOSTSW_OWN_ACPI 0 +#define HOSTSW_OWN_GPIO 1 +#define PAD_CFG_DW_OFFSET 0x400 + /* PADRSTCFG - when to reset the pad config */ +#define PADRSTCFG_SHIFT 30 +#define PADRSTCFG_MASK 0x3 +#define PADRSTCFG_DSW_PWROK 0 +#define PADRSTCFG_DEEP 1 +#define PADRSTCFG_PLTRST 2 +#define PADRSTCFG_RSMRST 3 + /* RXPADSTSEL - raw signal or internal state */ +#define RXPADSTSEL_SHIFT 29 +#define RXPADSTSEL_MASK 0x1 +#define RXPADSTSEL_RAW 0 +#define RXPADSTSEL_INTERNAL 1 + /* RXRAW1 - drive 1 instead instead of pad value */ +#define RXRAW1_SHIFT 28 +#define RXRAW1_MASK 0x1 +#define RXRAW1_NO 0 +#define RXRAW1_YES 1 + /* RXEVCFG - Interrupt and wake types */ +#define RXEVCFG_SHIFT 25 +#define RXEVCFG_MASK 0x3 +#define RXEVCFG_LEVEL 0 +#define RXEVCFG_EDGE 1 +#define RXEVCFG_DRIVE0 2 + /* PREGFRXSEL - use filtering on Rx pad */ +#define PREGFRXSEL_SHIFT 24 +#define PREGFRXSEL_MASK 0x1 +#define PREGFRXSEL_NO 0 +#define PREGFRXSEL_YES 1 + /* RXINV - invert signal to SMI, SCI, NMI, or IRQ routing. */ +#define RXINV_SHIFT 23 +#define RXINV_MASK 0x1 +#define RXINV_NO 0 +#define RXINV_YES 1 + /* GPIROUTIOXAPIC - route to io-xapic or not */ +#define GPIROUTIOXAPIC_SHIFT 20 +#define GPIROUTIOXAPIC_MASK 0x1 +#define GPIROUTIOXAPIC_NO 0 +#define GPIROUTIOXAPIC_YES 1 + /* GPIROUTSCI - route to SCI */ +#define GPIROUTSCI_SHIFT 19 +#define GPIROUTSCI_MASK 0x1 +#define GPIROUTSCI_NO 0 +#define GPIROUTSCI_YES 1 + /* GPIROUTSMI - route to SMI */ +#define GPIROUTSMI_SHIFT 18 +#define GPIROUTSMI_MASK 0x1 +#define GPIROUTSMI_NO 0 +#define GPIROUTSMI_YES 1 + /* GPIROUTNMI - route to NMI */ +#define GPIROUTNMI_SHIFT 17 +#define GPIROUTNMI_MASK 0x1 +#define GPIROUTNMI_NO 0 +#define GPIROUTNMI_YES 1 + /* PMODE - mode of pad */ +#define PMODE_SHIFT 10 +#define PMODE_MASK 0x3 +#define PMODE_GPIO 0 +#define PMODE_NF1 1 +#define PMODE_NF2 2 +#define PMODE_NF3 3 + /* GPIORXDIS - Disable Rx */ +#define GPIORXDIS_SHIFT 9 +#define GPIORXDIS_MASK 0x1 +#define GPIORXDIS_NO 0 +#define GPIORXDIS_YES 1 + /* GPIOTXDIS - Disable Tx */ +#define GPIOTXDIS_SHIFT 8 +#define GPIOTXDIS_MASK 0x1 +#define GPIOTXDIS_NO 0 +#define GPIOTXDIS_YES 1 + /* GPIORXSTATE - Internal state after glitch filter */ +#define GPIORXSTATE_SHIFT 1 +#define GPIORXSTATE_MASK 0x1 + /* GPIOTXSTATE - Drive value onto pad */ +#define GPIOTXSTATE_SHIFT 0 +#define GPIOTXSTATE_MASK 0x1 +#define PAD_CFG_DW_OFFSET 0x400 + /* TERM - termination control */ +#define PAD_TERM_SHIFT 10 +#define PAD_TERM_MASK 0xf +#define PAD_TERM_NONE 0 +#define PAD_TERM_5K_PD 2 +#define PAD_TERM_20K_PD 4 +#define PAD_TERM_1K_PU 9 +#define PAD_TERM_2K_PU 11 +#define PAD_TERM_5K_PU 10 +#define PAD_TERM_20K_PU 12 +#define PAD_TERM_667_PU 13 +#define PAD_TERM_NATIVE 15 + /* TOL - voltage tolerance */ +#define PAD_TOL_SHIFT 25 +#define PAD_TOL_MASK 0x1 +#define PAD_TOL_3V3 0 /* 3.3V default */ +#define PAD_TOL_1V8 1 /* 1.8V tolerant */ + +#define GPI_GPE_STS_OFFSET 0x140 +#define GPI_GPE_EN_OFFSET 0x160 +#define GPI_SMI_STS_OFFSET 0x180 +#define GPI_SMI_EN_OFFSET 0x1a0 +#else + /* * There are 8 GPIO groups. GPP_A -> GPP_G and GPD. GPD is the special case * where that group is not so generic. So most of the fixed numbers and macros @@ -504,5 +1041,5 @@ #define GPI_GPE_EN_OFFSET 0x160 #define GPI_SMI_STS_OFFSET 0x180 #define GPI_SMI_EN_OFFSET 0x1a0 - +#endif #endif /* _SOC_GPIO_DEFS_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h index be8ba79..dbb83ca 100644 --- a/src/soc/intel/skylake/include/soc/pei_data.h +++ b/src/soc/intel/skylake/include/soc/pei_data.h @@ -47,6 +47,8 @@ struct pei_data { /* Console output function */ tx_byte_func tx_byte; + /* Set to 0 for memory down */ + uint8_t spd_addresses[4]; /* * DIMM SPD data for memory down configurations * [CHANNEL][SLOT][SPD]
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Martin Roth