New patch to review for coreboot: northbridge/amd/agesa/family14: Remove commented code

[HAOUAS Elyes]

HAOUAS Elyes ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16895

-gerrit

commit e3129c34ab798284bec77c1853538fb2df64c26b
Author: Elyes HAOUAS 
Date:   Wed Oct 5 19:41:12 2016 +0200

northbridge/amd/agesa/family14: Remove commented code

Change-Id: I04fe6b7a8798d0f3cb54130283ce5a50eb9ac5b4
    Signed-off-by: Elyes HAOUAS 
---
 src/northbridge/amd/agesa/family14/amdfam14_conf.c | 34 ----------------------
 src/northbridge/amd/agesa/family14/northbridge.c   | 27 -----------------
 2 files changed, 61 deletions(-)

diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c
index dda6bf9..0e588ad 100644
--- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c
+++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c
@@ -84,34 +84,11 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 #if !defined(__PRE_RAM__)
 static u32 get_io_addr_index(u32 nodeid, u32 linkn)
 {
-#if 0
-	u32 index;
-
-	for (index = 0; index < 256; index++) {
-		if (sysconf.conf_io_addrx[index+4] == 0) {
-			sysconf.conf_io_addr[index+4] =  (nodeid & 0x3f);
-			sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
-			return index;
-		 }
-	 }
-#endif
     return	 0;
 }

static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
 {
-#if 0
-	u32 index;
-
-	for (index = 0; index < 64; index++) {
-		if (sysconf.conf_mmio_addrx[index+8] == 0) {
-			sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f);
-			sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
-			return index;
-		}
-	}
-#endif
-
    return	 0;
 }

@@ -125,17 +102,6 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
    pci_write_config32(__f1_dev[0], reg+4, tempreg);

tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4));	      //base :ISA and VGA ?
-#if 0
-	// FIXME: can we use VGA reg instead?
-	if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-		printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
-			__func__, dev_path(dev), link);
-		tempreg |= PCI_IO_BASE_VGA_EN;
-	}
-	if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
-		tempreg |= PCI_IO_BASE_NO_ISA;
-	}
-#endif
    pci_write_config32(__f1_dev[0], reg, tempreg);
 }

diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 4f10564..21978f6 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -36,7 +36,6 @@
 #include <sb_cimx.h>
 #endif

-//#define FX_DEVS NODE_NUMS
 #define FX_DEVS 1

static device_t __f0_dev[FX_DEVS];
@@ -280,32 +279,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
    		mem_hole.node_id = 0;	// record the node No with hole
    	}
    }
-#if 0
-	/* We need to double check if there is special set on base reg and limit reg
-	 * are not continuous instead of hole, it will find out its hole_startk.
-	 */
-	if (mem_hole.node_id == -1) {
-		resource_t limitk_pri = 0;
-		struct dram_base_mask_t d;
-		resource_t base_k, limit_k;
-		d = get_dram_base_mask(0);
-		if (d.base & 1) {
-			base_k = ((resource_t) (d.base & 0x1fffff00)) << 9;
-			if (base_k <= 4 * 1024 * 1024) {
-				if (limitk_pri != base_k) {	// we find the hole
-					mem_hole.hole_startk = (unsigned)limitk_pri;	// must be below 4G
-					mem_hole.node_id = 0;
-				}
-			}
-
-			limit_k =
-			    ((resource_t) ((d.mask + 0x00000100) & 0x1fffff00))
-			    << 9;
-			limitk_pri = limit_k;
-		}
-	}
-#endif
-
    return mem_hole;
 }
 #endif