Change in coreboot[master]: soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Hung-Te Lin, Rex-BC Chen.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64038 )

Change subject: soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF
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Patch Set 1: Code-Review+2

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/64038/comment/47c69bdb_9d64b13d 
PS1, Line 9: We encountered a delay issue when powering down. The root cause is
           : the incorrect setting for delay time.
           : 
           : The meaning of PMIC_CPSDSA4[4:0] is: power down at specified time slot.
           : If PMIC_CPSDSA4[4:0] is 0xA, in this time slot, it cause delay 20ms
           : comparing with 0xF.
           : 
           : To resolve this issue, we need to change to correct time slot.
           : Therefore, we change the value from 0xA to 0xF.
PMIC_CPSDSA4[4:0] controls the power-down at the specified time slot. Setting it to 0xA would cause an extra delay of 20ms compared to 0xF.

To avoid the delay, change the value from 0xA to 0xF.