Change in coreboot[master]: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA - coreboot-gerrit

2 Nov 2021


      Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58707 )
Change subject: soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA
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Patch Set 7: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec
Gerrit-Change-Number: 58707
Gerrit-PatchSet: 7
Gerrit-Owner: Raul Rangel rrangel@chromium.org
Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de
Gerrit-Reviewer: Jason Glenesk jason.glenesk@gmail.com
Gerrit-Reviewer: Julius Werner jwerner@chromium.org
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