Change in ...coreboot[master]: nb/intel/haswell: Add support for PCIe graphics

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30272 )

Change subject: nb/intel/haswell: Add support for PCIe graphics
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Patch Set 6:

(1 comment)

https://review.coreboot.org/#/c/30272/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/30272/6//COMMIT_MSG@11 
PS6, Line 11: *The first path*: If it's okay for the IGD to be disabled, the link
            : training is done in early romstage. The MRC will then set (and lock)
            : GGC, and, if there is a device of VGA class present in a PEG slot,
            : disable the IGD:
            : 
            : 	Before the MRC: GGC = 0x0208, DEVEN = 0x00000039.
            : 	After the MRC:  GGC = 0x0003, DEVEN = 0x00000029.
            : 
            : *The second path*: If the IGD needs to be kept enabled, the link
            : training is done in ramstage. This is because the MRC will always
            : disable the IGD if there is a device of VGA class in a PEG slot, but
            : it can't see the device until link training is done.
            : 
            : The second path can, unfortunately, lead to an increase in boot time, as
            : the training needs to be complete before the PEG bus is scanned. When
            : there are multiple PEG devices, the training occurs in parallel, limiting
            : the impact on boot time.
Would the following work?
- do link training in romstage.
- Setup the bridge and if you find a VGA class, disable that PEG with DEVEN, unless you have no IGD
- re-enable that PEG after the mrc.bin has run. (not sure if trainig is needed again)

That would provide a more unified flow and avoid different paths.