[S] Change in coreboot[master]: soc/intel/xeon_sp: select SCO_INTEL_COMMON_BLOCK_TCO

[Martin L Roth (Code Review)]

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71141 )

Change subject: soc/intel/xeon_sp: select SCO_INTEL_COMMON_BLOCK_TCO
......................................................................

soc/intel/xeon_sp: select SCO_INTEL_COMMON_BLOCK_TCO

Also disable TCO timer through calling tco_configure().

If tco_configure() is not called, the TCO timeout would
trigger SMI periodically about every 2 seconds with SMM log:
"TCO_STS: BIT18 TIMEOUT"

Tested=On AC CRB, does not see periodic SMI log.

Signed-off-by: Johnny Lin 
Change-Id: I2d307ad16109ae11862dd5e5acc0f12f47b22582
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71141
Tested-by: build bot (Jenkins) 
Reviewed-by: Marc Jones 
---
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/bootblock.c
2 files changed, 27 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Marc Jones: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 91b1569..784fd2e 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -47,12 +47,13 @@
    select SOC_INTEL_COMMON
    select SOC_INTEL_COMMON_RESET
    select SOC_INTEL_COMMON_BLOCK
+	select SOC_INTEL_COMMON_BLOCK_ACPI
    select SOC_INTEL_COMMON_BLOCK_CPU
    select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
    select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
    select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
    select SOC_INTEL_COMMON_BLOCK_SMM
-	select SOC_INTEL_COMMON_BLOCK_ACPI
+	select SOC_INTEL_COMMON_BLOCK_TCO
    select SOC_INTEL_COMMON_PCH_SERVER
    select SUPPORT_CPU_UCODE_IN_CBFS
    select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c
index 5ea09ac..ba215d8 100644
--- a/src/soc/intel/xeon_sp/bootblock.c
+++ b/src/soc/intel/xeon_sp/bootblock.c
@@ -4,6 +4,7 @@
 #include <device/pci.h>
 #include <FsptUpd.h>
 #include <intelblocks/fast_spi.h>
+#include <intelblocks/tco.h>
 #include <soc/iomap.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
@@ -73,4 +74,7 @@
    	intel_cbnt_log_registers();

bootblock_pch_init();
+
+	/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
+	tco_configure();
 }