Jonathan A. Kollasch (jakllsch@kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12304
-gerrit
commit fadf62c02d42401ebb2ef7758dd80a337282abed Author: Jonathan A. Kollasch jakllsch@kollasch.net Date: Tue Nov 3 10:06:38 2015 -0600
Initial Sun Ultra 40 M2 board port
Change-Id: I5b62ade908ffeb80e22f14edbe4c1ec04880bd30 Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net --- src/mainboard/sunw/ultra40m2/Kconfig | 18 +++-- src/mainboard/sunw/ultra40m2/Kconfig.name | 4 +- src/mainboard/sunw/ultra40m2/board_info.txt | 7 +- src/mainboard/sunw/ultra40m2/cmos.layout | 2 +- src/mainboard/sunw/ultra40m2/devicetree.cb | 109 ++++++++++------------------ src/mainboard/sunw/ultra40m2/hda_verb.c | 26 +++---- src/mainboard/sunw/ultra40m2/mptable.c | 2 +- src/mainboard/sunw/ultra40m2/resourcemap.c | 4 +- src/mainboard/sunw/ultra40m2/romstage.c | 24 +++--- 9 files changed, 84 insertions(+), 112 deletions(-)
diff --git a/src/mainboard/sunw/ultra40m2/Kconfig b/src/mainboard/sunw/ultra40m2/Kconfig index b5e51c5..2913ae8 100644 --- a/src/mainboard/sunw/ultra40m2/Kconfig +++ b/src/mainboard/sunw/ultra40m2/Kconfig @@ -1,4 +1,4 @@ -if BOARD_NVIDIA_L1_2PVV +if BOARD_SUNW_ULTRA40M2
config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -10,19 +10,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA - select SUPERIO_WINBOND_W83627EHG + select SUPERIO_SMSC_DME1737 select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_512 + select BOARD_ROMSIZE_KB_1024 select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE
config MAINBOARD_DIR string - default nvidia/l1_2pvv + default sunw/ultra40m2
config DCACHE_RAM_BASE hex @@ -46,7 +46,7 @@ config MCP55_NUM
config MAINBOARD_PART_NUMBER string - default "l1_2pvv" + default "Ultra 40 M2"
config MAX_CPUS int @@ -70,6 +70,10 @@ config IRQ_SLOT_COUNT
config MCP55_PCI_E_X_0 int - default 2 + default 1 + +config MCP55_PCI_E_X_1 + int + default 1
-endif # BOARD_NVIDIA_L1_2PVV +endif # BOARD_SUNW_ULTRA40M2 diff --git a/src/mainboard/sunw/ultra40m2/Kconfig.name b/src/mainboard/sunw/ultra40m2/Kconfig.name index 40dffc6..f6bc551 100644 --- a/src/mainboard/sunw/ultra40m2/Kconfig.name +++ b/src/mainboard/sunw/ultra40m2/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_NVIDIA_L1_2PVV - bool "l1_2pvv" +config BOARD_SUNW_ULTRA40M2 + bool "Ultra 40 M2" diff --git a/src/mainboard/sunw/ultra40m2/board_info.txt b/src/mainboard/sunw/ultra40m2/board_info.txt index b351b8e..b68555c 100644 --- a/src/mainboard/sunw/ultra40m2/board_info.txt +++ b/src/mainboard/sunw/ultra40m2/board_info.txt @@ -1 +1,6 @@ -Category: eval +Board URL: http://docs.oracle.com/cd/E19127-01/ultra40.ws/820-0123-13/intro.html +Board name: Ultra 40 M2 +Category: desktop +ROM package: PLCC +ROM protocol: LPC +ROM socketed: y diff --git a/src/mainboard/sunw/ultra40m2/cmos.layout b/src/mainboard/sunw/ultra40m2/cmos.layout index 53f259a..3dfdf35 100644 --- a/src/mainboard/sunw/ultra40m2/cmos.layout +++ b/src/mainboard/sunw/ultra40m2/cmos.layout @@ -25,7 +25,7 @@ entries 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock 399 1 e 2 multi_core -400 1 e 1 power_on_after_fail +408 1 e 1 power_on_after_fail 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi diff --git a/src/mainboard/sunw/ultra40m2/devicetree.cb b/src/mainboard/sunw/ultra40m2/devicetree.cb index 5709db7..9928d45 100644 --- a/src/mainboard/sunw/ultra40m2/devicetree.cb +++ b/src/mainboard/sunw/ultra40m2/devicetree.cb @@ -5,66 +5,45 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device domain 0 on # PCI domain - subsystemid 0x1022 0x2b80 inherit + subsystemid 0x108e 0x6676 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 + device pci 18.0 on end # Link 0 == LDT 0 + device pci 18.0 on # Link 1 == LDT 1 chip southbridge/nvidia/mcp55 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O + chip superio/smsc/dme1737 # Super I/O device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.3 off # Parallel port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 2 end - device pnp 2e.2 on # Com1 + device pnp 2e.4 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.5 off # COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard & mouse + device pnp 2e.7 on # PS/2 (connectors not populated) io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 off # MIDI - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 + device pnp 2e.a on # Runtime Registers + io 0x60 = 0x600 end end + # There's an Infineon SLB9635TT12 TPM on this LPC bus. + # There's also an Akom AK2001 7-segment port 0x80 decoder on + # this LPC bus. end device pci 1.1 on # SM 0 chip drivers/generic/generic # DIMM 0-0-0 @@ -93,41 +72,36 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end + #chip drivers/generic/generic # PCA9556 GPIO on HDD backplanes (address conflict!) + # device i2c 18 on end + #end + #chip drivers/generic/generic # EMC6D103 HWM (for CPUs) + # device i2c 2d on end + #end + #chip drivers/generic/generic # DME1737 HWM + # device i2c 2e on end + #end + #chip drivers/generic/generic # HDD 4-7 backplane FRU 24C64 EEPROM + # device i2c 51 on end + #end + #chip drivers/generic/generic # front panel module FRU 24C64 EEPROM + # device i2c 52 on end + #end + #chip drivers/generic/generic # HDD 0-3 backplane FRU 24C64 EEPROM + # device i2c 53 on end + #end + # there are more SMbus devices on this bus end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 + device pci 5.2 off end # SATA 2 device pci 6.0 on end # PCI device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC + device pci 8.0 off end # NIC + device pci 9.0 off end # NIC device pci a.0 on end # PCI E 5 device pci b.0 off end # PCI E 4 device pci c.0 off end # PCI E 3 @@ -137,12 +111,8 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end end - device pci 18.0 on end # Link 1 device pci 18.0 on # Link 2 == LDT 2 chip southbridge/nvidia/mcp55 # Southbridge device pci 0.0 on end # HT @@ -153,7 +123,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 4.0 off end # IDE device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 + device pci 5.2 off end # SATA 2 device pci 6.0 off end # PCI device pci 6.1 off end # AZA device pci 8.0 on end # NIC @@ -162,14 +132,11 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci b.0 off end # PCI E 4 device pci c.0 off end # PCI E 3 device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 + device pci e.0 off end # PCI E 1 device pci f.0 on end # PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end end device pci 18.1 on end diff --git a/src/mainboard/sunw/ultra40m2/hda_verb.c b/src/mainboard/sunw/ultra40m2/hda_verb.c index 31052f2..137196c 100644 --- a/src/mainboard/sunw/ultra40m2/hda_verb.c +++ b/src/mainboard/sunw/ultra40m2/hda_verb.c @@ -19,18 +19,18 @@
const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0880, // Codec Vendor / Device ID: Realtek ALC880 + 0x10ec0885, // Codec Vendor / Device ID: Realtek ALC889A 0x00000000, // Subsystem ID 0x0000000d, // Number of jacks
- /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x0000e601 */ - AZALIA_SUBVENDOR(0x0, 0x0000e601), + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x108ee601 */ + AZALIA_SUBVENDOR(0x0, 0x108ee601),
/* NID 0x14, FRONT-OUT-L/R */ - AZALIA_PIN_CFG(0x0, 0x14, 0x01014410), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014010),
/* NID 0x15, SURR-OUT-L/R */ - AZALIA_PIN_CFG(0x0, 0x15, 0x01011412), + AZALIA_PIN_CFG(0x0, 0x15, 0x01011012),
/* NID 0x16, CEN/LFE-OUT */ AZALIA_PIN_CFG(0x0, 0x16, 0x01016011), @@ -39,28 +39,28 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0x0, 0x17, 0x01012014),
/* NID 0x18, MIC1-L/R, VREFO */ - AZALIA_PIN_CFG(0x0, 0x18, 0x01a19c30), + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19840),
/* NID 0x19, MIC2-L/R, VREFO */ - AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c40), + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19850),
/* NID 0x1a, LINE1-L/R, VREFO */ - AZALIA_PIN_CFG(0x0, 0x1a, 0x01813431), + AZALIA_PIN_CFG(0x0, 0x1a, 0x01813041),
/* NID 0x1b, LINE2-L/R, VREFO */ - AZALIA_PIN_CFG(0x0, 0x1b, 0x0221441f), + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214020),
/* NID 0x1c, CD-L/R / GND */ - AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1c, 0x9933014f),
/* NID 0x1d, PCBEEP */ - AZALIA_PIN_CFG(0x0, 0x1d, 0x9983013e), + AZALIA_PIN_CFG(0x0, 0x1d, 0x99830142),
/* NID 0x1e, S/PDIF-OUT */ - AZALIA_PIN_CFG(0x0, 0x1e, 0x01454120), + AZALIA_PIN_CFG(0x0, 0x1e, 0x014b4130),
/* NID 0x1f, S/PDIF-IN */ - AZALIA_PIN_CFG(0x0, 0x1f, 0x01c59150), + AZALIA_PIN_CFG(0x0, 0x1f, 0x01cb9160), };
const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/sunw/ultra40m2/mptable.c b/src/mainboard/sunw/ultra40m2/mptable.c index d000b1a..89bb9eb 100644 --- a/src/mainboard/sunw/ultra40m2/mptable.c +++ b/src/mainboard/sunw/ultra40m2/mptable.c @@ -130,7 +130,7 @@ static void *smp_write_config_table(void *v) dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0)); if (dev && dev->enabled) { for (i = 0; i < 4; i++) - apicpin[i] = 0x10 + (2+i)%4; + apicpin[i] = 0x10 + i%4; smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin); } } diff --git a/src/mainboard/sunw/ultra40m2/resourcemap.c b/src/mainboard/sunw/ultra40m2/resourcemap.c index 2950687..5235b0d 100644 --- a/src/mainboard/sunw/ultra40m2/resourcemap.c +++ b/src/mainboard/sunw/ultra40m2/resourcemap.c @@ -194,7 +194,7 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, +// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007010, // PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -265,7 +265,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000103, /* link 1 of cpu 0 --> Nvidia MCP55 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 4186cc7..1006f19 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -32,14 +32,13 @@ #include "lib/delay.c" #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627ehg/w83627ehg.h> +#include <superio/smsc/dme1737/dme1737.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c"
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -57,13 +56,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c"
+#define NMI_SC 0x0061 +#define PCI_SERR_EN 0x04 + #define MCP55_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+61, 0x00, 0x05,/* GPIO62: enable/not-disable on-board TSB43AB22A Firewire */
#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" @@ -114,13 +111,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0); - pnp_exit_ext_func_mode(SERIAL_DEV); - setup_mb_resource_map();
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + dme1737_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init();
/* Halt if there was a built in self test failure */ @@ -169,6 +162,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x();
+ /* mask NMI from constantly-asserted-on-this-board SERR# */ + outb((inb(NMI_SC) & 0x0f) | PCI_SERR_EN, NMI_SC); + // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { printk(BIOS_INFO, "ht reset -\n");
-
Jonathan A. Kollasch