[M] Change in coreboot[main]: soc/intel/xeon_sp: Generate root port SSDT device objects

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak.

Hello Jincheng Li,

I'd like you to do a code review.
Please visit

    https://review.coreboot.org/c/coreboot/+/81567?usp=email

to review the following change.


Change subject: soc/intel/xeon_sp: Generate root port SSDT device objects
......................................................................

soc/intel/xeon_sp: Generate root port SSDT device objects

PCIe root port devices are Root Complex Integrated End Points (RCiEP)
PCIe bridges under IIO stacks. Create SSDT device objects for them
and write _ADR and _BBN.

Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e
Signed-off-by: Shuo Liu <[e-mail]>
Signed-off-by: Jincheng Li <[e-mail]>
---
M src/acpi/acpigen_pci.c
M src/include/acpi/acpigen_pci.h
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/gnr/soc_acpi.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
5 files changed, 55 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/81567/1

diff --git a/src/acpi/acpigen_pci.c b/src/acpi/acpigen_pci.c
index a23b84c..427fb49 100644
--- a/src/acpi/acpigen_pci.c
+++ b/src/acpi/acpigen_pci.c
@@ -360,3 +360,19 @@
 	 */
 	return 0;
 }
+
+void acpigen_write_pci_root_ports(const struct device *domain)
+{
+	struct device *dev = NULL;
+	while ((dev = dev_bus_each_child(domain->downstream, dev))) {
+		if (!is_pci_bridge(dev))
+			continue;
+		const char *name = acpi_device_name(dev);
+		if (!name)
+			continue;
+		acpigen_write_device(name);
+		acpigen_write_BBN(dev->downstream->secondary);
+		acpigen_write_ADR_pci_device(dev);
+		acpigen_pop_len();
+	}
+}
diff --git a/src/include/acpi/acpigen_pci.h b/src/include/acpi/acpigen_pci.h
index 7a07423..5b5d473 100644
--- a/src/include/acpi/acpigen_pci.h
+++ b/src/include/acpi/acpigen_pci.h
@@ -27,4 +27,6 @@
 uint32_t soc_get_granted_pci_features(const struct device *domain);
 uint32_t soc_get_granted_cxl_features(const struct device *domain);
 
+void acpigen_write_pci_root_ports(const struct device *domain);
+
 #endif /* ACPIGEN_PCI_H */
diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c
index 9ee8d6a..dcba092 100644
--- a/src/soc/intel/xeon_sp/acpi.c
+++ b/src/soc/intel/xeon_sp/acpi.c
@@ -148,11 +148,43 @@
 	dev->name = name;
 }
 
+static struct device_operations pci_root_port_ops = {
+	.acpi_name = &soc_acpi_name,
+};
+
+static void pci_root_port_set_acpi_name(struct device *dev, uint8_t id)
+{
+	if (!is_pci_bridge(dev))
+		return;
+
+	assert(id < 8);
+
+	char *name = xmalloc(ACPI_NAME_BUFFER_SIZE);
+	snprintf(name, ACPI_NAME_BUFFER_SIZE, "RP%02X", id);
+	dev->name = name;
+	dev->ops = &pci_root_port_ops;
+}
+
+void iio_domain_set_root_port_acpi_names(const struct device *domain)
+{
+	struct device *dev = NULL;
+	uint8_t id = 0;
+	while ((dev = dev_bus_each_child(domain->downstream, dev))) {
+		if (!is_pci_bridge(dev))
+			continue;
+		pci_root_port_set_acpi_name(dev, id++);
+		dev->ops = &pci_root_port_ops;
+	}
+}
+
 const char *soc_acpi_name(const struct device *dev)
 {
 	if (dev->path.type == DEVICE_PATH_DOMAIN)
 		return dev->name;
 
+	if (is_pci_bridge(dev))
+		return dev->name;
+
 	/* FIXME: Add SoC specific device names here */
 
 	return NULL;
diff --git a/src/soc/intel/xeon_sp/gnr/soc_acpi.c b/src/soc/intel/xeon_sp/gnr/soc_acpi.c
index 29bb51a..d8160fc 100644
--- a/src/soc/intel/xeon_sp/gnr/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/gnr/soc_acpi.c
@@ -103,6 +103,10 @@
 	/* _OSC */
 	acpigen_write_OSC_pci_domain(domain, is_cxl_domain(domain));
 
+	/* RP0X */
+	iio_domain_set_root_port_acpi_names(domain);
+	acpigen_write_pci_root_ports(domain);
+
 	acpigen_pop_len();
 	acpigen_pop_len();
 }
diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h
index e374544..7ab681e 100644
--- a/src/soc/intel/xeon_sp/include/soc/acpi.h
+++ b/src/soc/intel/xeon_sp/include/soc/acpi.h
@@ -24,5 +24,6 @@
 unsigned long cxl_fill_srat(unsigned long current);
 
 void iio_domain_set_acpi_name(struct device *dev, const char *prefix);
+void iio_domain_set_root_port_acpi_names(const struct device *domain);
 
 #endif /* _SOC_ACPI_H_ */

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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e
Gerrit-Change-Number: 81567
Gerrit-PatchSet: 1
Gerrit-Owner: Shuo Liu <[e-mail]>
Gerrit-Reviewer: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Christian Walter <[e-mail]>
Gerrit-Reviewer: Cliff Huang <[e-mail]>
Gerrit-Reviewer: Jincheng Li <[e-mail]>
Gerrit-Reviewer: Johnny Lin <[e-mail]>
Gerrit-Reviewer: Jonathan Zhang <[e-mail]>
Gerrit-Reviewer: Lance Zhao <[e-mail]>
Gerrit-Reviewer: Lean Sheng Tan <[e-mail]>
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