Change in coreboot[master]: soc/amd/picasso/acpi: remove AOAC device enables from global NVS
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44245 ) Change subject: soc/amd/picasso/acpi: remove AOAC device enables from global NVS ...................................................................... soc/amd/picasso/acpi: remove AOAC device enables from global NVS These values in GNVS are written, but never read/used. aoac.asl contains proper ACPI power management functions for the AOAC devices that directly access the state from the device's registers instead of relying on cached values in GNVS, so the corresponding GNVS entries can be dropped. BUG=b:161165393 TEST=Mandolin still boots and dmesg shows no new ACPI errors. Change-Id: Iee78df215308bd9b656228be787fac121d10ca99 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> --- M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/picasso/southbridge.c 3 files changed, 1 insertion(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44245/1 diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 6e63b8d..6790a5f 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -25,19 +25,6 @@ TMPS, 8, // 0x17 - Temperature Sensor ID TCRT, 8, // 0x18 - Critical Threshold TPSV, 8, // 0x19 - Passive Threshold - Offset (0x20), // 0x20 - AOAC Device Enables - , 7, - IC2E, 1, // I2C2, 7 - IC3E, 1, // I2C3, 8 - IC4E, 1, // I2C4, 9 - , 1, - UT0E, 1, // UART0, 11 - UT1E, 1, // UART1, 12 - , 3, - UT2E, 1, // UART2, 16 - , 9, - UT23, 1, // UART3, 26 - ESPI, 1, // ESPI, 27 /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index b6708c8..2abcdd3 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -25,9 +25,7 @@ uint8_t tmps; /* 0x17 - Temperature Sensor ID */ uint8_t tcrt; /* 0x18 - Critical Threshold */ uint8_t tpsv; /* 0x19 - Passive Threshold */ - uint8_t pad1[6]; - aoac_devs_t aoac; /* 0x20 - AOAC device enables */ - uint8_t unused[220]; + uint8_t unused[230]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 54d7640..0b45c10 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -347,22 +347,6 @@ al2ahb_clock_gate(); } -static void set_sb_final_nvs(void) -{ - struct global_nvs *gnvs = acpi_get_gnvs(); - if (gnvs == NULL) - return; - - gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); - gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); - gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C4); - gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); - gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); - gnvs->aoac.ut2e = is_aoac_device_enabled(FCH_AOAC_DEV_UART2); - gnvs->aoac.ut3e = is_aoac_device_enabled(FCH_AOAC_DEV_UART3); - gnvs->aoac.espi = 1; -} - void southbridge_final(void *chip_info) { uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; @@ -370,8 +354,6 @@ if (CONFIG(MAINBOARD_POWER_RESTORE)) restored_power = PM_RESTORE_S0_IF_PREV_S0; pm_write8(PM_RTC_SHADOW, restored_power); - - set_sb_final_nvs(); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/44245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee78df215308bd9b656228be787fac121d10ca99 Gerrit-Change-Number: 44245 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot@felixheld.de> Gerrit-MessageType: newchange
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44245 ) Change subject: soc/amd/picasso/acpi: remove AOAC device enables from global NVS ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee78df215308bd9b656228be787fac121d10ca99 Gerrit-Change-Number: 44245 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot@felixheld.de> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk@gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel@chromium.org> Gerrit-Comment-Date: Wed, 05 Aug 2020 19:57:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44245 ) Change subject: soc/amd/picasso/acpi: remove AOAC device enables from global NVS ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee78df215308bd9b656228be787fac121d10ca99 Gerrit-Change-Number: 44245 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot@felixheld.de> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk@gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel@chromium.org> Gerrit-Comment-Date: Wed, 05 Aug 2020 20:01:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44245 ) Change subject: soc/amd/picasso/acpi: remove AOAC device enables from global NVS ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee78df215308bd9b656228be787fac121d10ca99 Gerrit-Change-Number: 44245 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot@felixheld.de> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk@gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel@chromium.org> Gerrit-Comment-Date: Wed, 05 Aug 2020 20:05:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44245 ) Change subject: soc/amd/picasso/acpi: remove AOAC device enables from global NVS ...................................................................... soc/amd/picasso/acpi: remove AOAC device enables from global NVS These values in GNVS are written, but never read/used. aoac.asl contains proper ACPI power management functions for the AOAC devices that directly access the state from the device's registers instead of relying on cached values in GNVS, so the corresponding GNVS entries can be dropped. BUG=b:161165393 TEST=Mandolin still boots and dmesg shows no new ACPI errors. Change-Id: Iee78df215308bd9b656228be787fac121d10ca99 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> --- M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/picasso/southbridge.c 3 files changed, 1 insertion(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Raul Rangel: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 6e63b8d..6790a5f 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -25,19 +25,6 @@ TMPS, 8, // 0x17 - Temperature Sensor ID TCRT, 8, // 0x18 - Critical Threshold TPSV, 8, // 0x19 - Passive Threshold - Offset (0x20), // 0x20 - AOAC Device Enables - , 7, - IC2E, 1, // I2C2, 7 - IC3E, 1, // I2C3, 8 - IC4E, 1, // I2C4, 9 - , 1, - UT0E, 1, // UART0, 11 - UT1E, 1, // UART1, 12 - , 3, - UT2E, 1, // UART2, 16 - , 9, - UT23, 1, // UART3, 26 - ESPI, 1, // ESPI, 27 /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index b6708c8..2abcdd3 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -25,9 +25,7 @@ uint8_t tmps; /* 0x17 - Temperature Sensor ID */ uint8_t tcrt; /* 0x18 - Critical Threshold */ uint8_t tpsv; /* 0x19 - Passive Threshold */ - uint8_t pad1[6]; - aoac_devs_t aoac; /* 0x20 - AOAC device enables */ - uint8_t unused[220]; + uint8_t unused[230]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 54d7640..0b45c10 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -347,22 +347,6 @@ al2ahb_clock_gate(); } -static void set_sb_final_nvs(void) -{ - struct global_nvs *gnvs = acpi_get_gnvs(); - if (gnvs == NULL) - return; - - gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); - gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); - gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C4); - gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); - gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); - gnvs->aoac.ut2e = is_aoac_device_enabled(FCH_AOAC_DEV_UART2); - gnvs->aoac.ut3e = is_aoac_device_enabled(FCH_AOAC_DEV_UART3); - gnvs->aoac.espi = 1; -} - void southbridge_final(void *chip_info) { uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; @@ -370,8 +354,6 @@ if (CONFIG(MAINBOARD_POWER_RESTORE)) restored_power = PM_RESTORE_S0_IF_PREV_S0; pm_write8(PM_RTC_SHADOW, restored_power); - - set_sb_final_nvs(); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/44245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee78df215308bd9b656228be787fac121d10ca99 Gerrit-Change-Number: 44245 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot@felixheld.de> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot@felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk@gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel@chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-MessageType: merged
participants (4)
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Aaron Durbin (Code Review) -
Angel Pons (Code Review)
-
Felix Held (Code Review)
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Raul Rangel (Code Review)