[M] Change in coreboot[main]: mb/google/rex/var/screebo: Override power limits

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79330?usp=email )

(

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/rex/var/screebo: Override power limits
......................................................................

mb/google/rex/var/screebo: Override power limits

This patch allows variants to override the default baseboard PLx
limits.

Additionally, rearrange the include header files alphabetically.

BUG=b:313667378
TEST=Able to boot google/screebo with modified power limits.

Before:

[DEBUG]  WEAK: src/mainboard/google/rex/variants/baseboard/rex/
         ramstage.c/variant_devtree_update called
[INFO ]  Overriding power limits PL1 (mW) (10000, 15000)
         PL2 (mW) (40000, 40000) PL4 (W) (84)

After:

[INFO ]  Overriding power limits PL1 (mW) (10000, 15000)
         PL2 (mW) (40000, 40000) PL4 (W) (84)

Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79330
Tested-by: build bot (Jenkins) 
Reviewed-by: Kapil Porwal 
---
M src/mainboard/google/rex/variants/screebo/variant.c
1 file changed, 65 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kapil Porwal: Looks good to me, approved

diff --git a/src/mainboard/google/rex/variants/screebo/variant.c b/src/mainboard/google/rex/variants/screebo/variant.c
index 1dd8b98..edddd43 100644
--- a/src/mainboard/google/rex/variants/screebo/variant.c
+++ b/src/mainboard/google/rex/variants/screebo/variant.c
@@ -1,8 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-#include <chip.h>
-#include <fw_config.h>
 #include <baseboard/variants.h>
+#include <chip.h>
+#include <ec/google/chromeec/ec.h>
+#include <fw_config.h>
 #include <sar.h>

const char *get_wifi_sar_cbfs_filename(void)
@@ -29,3 +30,65 @@
    	config->tcss_aux_ori = 0x04;
    }
 }
+
+const struct cpu_tdp_power_limits variant_perf_efficient_limits[] = {
+	{
+		.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
+		.cpu_tdp = 15,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 40000,
+		.pl2_max_power = 40000,
+		.pl4_power = 84000
+	},
+	{
+		.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
+		.cpu_tdp = 15,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 40000,
+		.pl2_max_power = 40000,
+		.pl4_power = 84000
+	},
+};
+
+const struct cpu_tdp_power_limits variant_power_efficient_limits[] = {
+	{
+		.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
+		.cpu_tdp = 15,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 40000,
+		.pl2_max_power = 40000,
+		.pl4_power = 47000
+	},
+	{
+		.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
+		.cpu_tdp = 15,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 40000,
+		.pl2_max_power = 40000,
+		.pl4_power = 47000
+	},
+};
+
+void variant_devtree_update(void)
+{
+	const struct cpu_tdp_power_limits *limits = variant_perf_efficient_limits;
+	size_t limits_size = ARRAY_SIZE(variant_perf_efficient_limits);
+
+	/*
+	 * If battery is not present or battery level is at or below critical threshold
+	 * to boot a platform with the performance efficient configuration, boot with
+	 * the power optimized configuration.
+	 */
+	if (CONFIG(EC_GOOGLE_CHROMEEC)) {
+		if (!google_chromeec_is_battery_present_and_above_critical_threshold()) {
+			limits = variant_power_efficient_limits;
+			limits_size = ARRAY_SIZE(variant_power_efficient_limits);
+		}
+	}
+
+	variant_update_cpu_power_limits(limits, limits_size);
+}