Patch set updated for coreboot: driver/intel/fsp2_0: Add version parameter to FSP platform callback
Andrey Petrov (andrey.petrov@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17497
-gerrit
commit a5e4e6d6d0052a621853c5780e92698874de7464 Author: Andrey Petrov andrey.petrov@intel.com Date: Fri Nov 18 14:57:51 2016 -0800
driver/intel/fsp2_0: Add version parameter to FSP platform callback
Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528 Signed-off-by: Andrey Petrov andrey.petrov@intel.com --- src/drivers/intel/fsp2_0/include/fsp/api.h | 2 +- src/drivers/intel/fsp2_0/memory_init.c | 2 +- src/soc/intel/apollolake/romstage.c | 2 +- src/soc/intel/quark/romstage/fsp2_0.c | 2 +- src/soc/intel/skylake/romstage/romstage_fsp20.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index b012040..a8445ba 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -41,7 +41,7 @@ void fsp_memory_init(bool s3wake); void fsp_silicon_init(bool s3wake);
/* Callbacks for updating stage-specific parameters */ -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd); +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
/* Callback after processing FSP notify */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b833561..56de0ef 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -316,7 +316,7 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, die("FSPM_ARCH_UPD not found!\n");
/* Give SoC and mainboard a chance to update the UPD */ - platform_fsp_memory_init_params_cb(&fspm_upd); + platform_fsp_memory_init_params_cb(&fspm_upd, hdr->fsp_revision);
/* Call FspMemoryInit */ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index f1d4b57..d623913 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -237,7 +237,7 @@ static void fill_console_params(FSPM_UPD *mupd) } }
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { fill_console_params(mupd); mainboard_memory_init_params(mupd); diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index d90bd38..17080a3 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -87,7 +87,7 @@ int fill_power_state(void) return ps->prev_sleep_state; }
-void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) { FSPM_ARCH_UPD *aupd; const struct device *dev; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8e08323..adb8442 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -132,7 +132,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) m_cfg->PcieRpEnableMask = mask; }
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
-
Andrey Petrov