Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504
-gerrit
commit 14e0cc726df3643d978b028b0a2f0a457898605f Author: Aaron Durbin adurbin@chromium.org Date: Thu Sep 3 11:29:28 2015 -0500
x86: add rosmtage.S to bind program flow and ordering
The build system was previously determining the flow of the romstage code by the order of files added to the crt0s make variable. Those files were then concatenated together, and the resulting file was added to the build dependencies for romstage proper.
Now romstage.S is added that can be built using the default object file rules. The generated romstage.inc is pulled in by way of an #include in the newly added romstage.S.
BUG=chrome-os-partner:44827 BRANCH=None TEST=Built vortex, rambi, and some asus boards. compared readelf -e output.
Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/arch/x86/Makefile.inc | 26 +++++++++++++------------- src/arch/x86/romstage.S | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 13 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8f8e4bc..f6379ab 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,17 +113,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
-crt0s = $(src)/arch/x86/prologue.inc romstage-srcs += $(src)/arch/x86/romstage.ld -crt0s += $(src)/cpu/x86/32bit/entry32.inc romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
-crt0s += $(src)/cpu/x86/fpu_enable.inc -ifeq ($(CONFIG_SSE),y) -crt0s += $(src)/cpu/x86/sse_enable.inc -endif +# Chipset specific assembly stubs in the romstage program flow. Certain +# boards have more than one assembly stub so collect those and put them +# into a single generated file. +crt0s = $(cpu_incs-y) + +$(objgenerated)/romstage.inc: $$(crt0s) + @printf " GEN $(subst $(obj)/,,$(@))\n" + printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-crt0s += $(cpu_incs-y) +# Add the assembly file that pulls in the rest of the dependencies in +# the right order. Make sure the auto generated romstage.inc is a proper +# dependency. +romstage-y += romstage.S +$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
ifneq ($(CONFIG_ROMCC),y)
@@ -165,8 +171,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/
endif
-romstage-srcs += $(objgenerated)/crt0.S - romstage-libs ?=
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) @@ -209,10 +213,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@
-$(objgenerated)/crt0.S: $$(crt0s) - @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@ - # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 romstage-S-ccopts += -I. -g0
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S new file mode 100644 index 0000000..b19b954 --- /dev/null +++ b/src/arch/x86/romstage.S @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* This file assembles the start of the romstage program by the order of the + * includes. Thus, it's extremely important that one pays very careful + * attention to the order of the includes. */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/32bit/entry32.inc> +#include <cpu/x86/fpu_enable.inc> +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * The romstage.inc is generated based on the requirements of the mainboard. + * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be + * processed by ROMCC and added. In non-ROMCC boards the chipsets' + * cache-as-ram setup files would be here. + */ +#include <generated/romstage.inc>
-
Aaron Durbin