Patch set updated for coreboot: google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16699

-gerrit

commit a9168662b358747aadc926fa8170b29f29022ac2
Author: Jeffy Chen 
Date:   Fri Sep 2 18:16:33 2016 +0800

google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration

Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto.

BUG=chrome-os-partner:56759
    BRANCH=none
    TEST=Build

Change-Id: I698fe450d48b64a06232aa44ecf91d688d9dc17a
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: d3edecdb135939c3264ab1b831e7821d3a3e0149
    Original-Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531
    Original-Signed-off-by: Jeffy Chen 
    Original-Reviewed-on: https://chromium-review.googlesource.com/380443
    Original-Commit-Ready: Alexandru Stan 
    Original-Tested-by: Alexandru Stan 
    Original-Reviewed-by: Alexandru Stan 
    Original-Reviewed-by: Jonathan Dixon 
    Original-Reviewed-by: Julius Werner 
---
 src/mainboard/google/veyron_rialto/sdram_configs.c |  2 +-
 .../sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc  | 77 ++++++++++++++++++++++
 2 files changed, 78 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c
index 42fa582..0e260c3 100644
--- a/src/mainboard/google/veyron_rialto/sdram_configs.c
+++ b/src/mainboard/google/veyron_rialto/sdram_configs.c
@@ -22,7 +22,7 @@

static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc"	/* ram_code = 0000 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0001 */
+#include "sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc"/* ram_code = 0001 */
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 0011 */
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 0100 */
diff --git a/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc
new file mode 100644
index 0000000..df3bb2a
--- /dev/null
+++ b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc
@@ -0,0 +1,77 @@
+{
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x0,
+			.col = 0x0,
+			.bk = 0x0,
+			.bw = 0x0,
+			.dbw = 0x0,
+			.row_3_4 = 0x0,
+			.cs0_row = 0x0,
+			.cs1_row = 0x0
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 3,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 1,
+	.stride = 22,
+	.odt = 0
+},