[S] Change in coreboot[master]: soc/amd/cezanne: remove LIDS field from global NVS

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72184 )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/amd/cezanne: remove LIDS field from global NVS
......................................................................

soc/amd/cezanne: remove LIDS field from global NVS

Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Cezanne SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.

Signed-off-by: Felix Held 
Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72184
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
---
M src/mainboard/google/guybrush/dsdt.asl
M src/soc/amd/cezanne/acpi/globalnvs.asl
M src/soc/amd/cezanne/include/soc/nvs.h
3 files changed, 27 insertions(+), 8 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved

diff --git a/src/mainboard/google/guybrush/dsdt.asl b/src/mainboard/google/guybrush/dsdt.asl
index 6c208cf..782bd9d 100644
--- a/src/mainboard/google/guybrush/dsdt.asl
+++ b/src/mainboard/google/guybrush/dsdt.asl
@@ -13,6 +13,9 @@
    )
 {
    #include <acpi/dsdt_top.asl>
+
+	Name(LIDS, 0)
+
    #include <soc.asl>

/* ChromeOS Embedded Controller */
diff --git a/src/soc/amd/cezanne/acpi/globalnvs.asl b/src/soc/amd/cezanne/acpi/globalnvs.asl
index bccce09..f4a6c5f 100644
--- a/src/soc/amd/cezanne/acpi/globalnvs.asl
+++ b/src/soc/amd/cezanne/acpi/globalnvs.asl
@@ -8,8 +8,7 @@
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
    /* Miscellaneous */
-	LIDS,	8,	// 0x00 - LID State
-	CBMC,	32,	// 0x01 - 0x04 - coreboot Memory Console
-	PM1I,	64,	// 0x05 - 0x0c - System Wake Source - PM1 Index
-	GPEI,	64,	// 0x0d - 0x14 - GPE Wake Source
+	CBMC,	32,	// 0x00 - 0x03 - coreboot Memory Console
+	PM1I,	64,	// 0x04 - 0x0b - System Wake Source - PM1 Index
+	GPEI,	64,	// 0x0c - 0x13 - GPE Wake Source
 }
diff --git a/src/soc/amd/cezanne/include/soc/nvs.h b/src/soc/amd/cezanne/include/soc/nvs.h
index d990f45..d1a8e30 100644
--- a/src/soc/amd/cezanne/include/soc/nvs.h
+++ b/src/soc/amd/cezanne/include/soc/nvs.h
@@ -13,10 +13,9 @@

struct __packed global_nvs {
    /* Miscellaneous */
-	uint8_t		lids; /* 0x00 - LID State */
-	uint32_t	cbmc; /* 0x01 - 0x04 - coreboot Memory Console */
-	uint64_t	pm1i; /* 0x05 - 0x0c - System Wake Source - PM1 Index */
-	uint64_t	gpei; /* 0x0d - 0x14 - GPE Wake Source */
+	uint32_t	cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
+	uint64_t	pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */
+	uint64_t	gpei; /* 0x0c - 0x13 - GPE Wake Source */
 };

#endif /* AMD_CEZANNE_NVS_H */