[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79167?usp=email )

Change subject: sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree
......................................................................

sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree

Since the LPC bridge in the PCH is always on the same device function,
the device operations can be statically assigned in the devicetree and
there's no need to bind the LPC bridge device operations to the PCI
device during runtime via a list of PCI IDs.

Signed-off-by: Felix Held 
Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79167
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Patrick Rudolph 
---
M src/northbridge/intel/sandybridge/chipset.cb
M src/southbridge/intel/bd82x6x/lpc.c
2 files changed, 2 insertions(+), 25 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, but someone else must approve
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb
index a08b1bd..83680c1 100644
--- a/src/northbridge/intel/sandybridge/chipset.cb
+++ b/src/northbridge/intel/sandybridge/chipset.cb
@@ -37,7 +37,7 @@
    		device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #8
    		device pci 1d.0 alias ehci1 off end      # USB2 EHCI #1
    		device pci 1e.0 alias pci_bridge off end # PCI bridge
-			device pci 1f.0 alias lpc on end         # LPC bridge
+			device pci 1f.0 alias lpc on ops bd82x6x_lpc_bridge_ops end
    		device pci 1f.2 alias sata1 off end      # SATA Controller 1
    		device pci 1f.3 alias smbus on end       # SMBus
    		device pci 1f.5 alias sata2 off end      # SATA Controller 2
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 0cf7b9c..5d1a7bf 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -658,7 +658,7 @@
    	memcpy(spi_config, &config->spi, sizeof(*spi_config));
 }

-static struct device_operations device_ops = {
+struct device_operations bd82x6x_lpc_bridge_ops = {
    .read_resources		= pch_lpc_read_resources,
    .set_resources		= pci_dev_set_resources,
    .enable_resources	= pci_dev_enable_resources,
@@ -671,26 +671,3 @@
    .scan_bus		= scan_static_bus,
    .ops_pci		= &pci_dev_ops_pci,
 };
-
-/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and
- * Intel C200 Series Chipset
- */
-
-static const unsigned short pci_device_ids[] = {
-	0x1c40, 0x1c41, 0x1c42, 0x1c43, 0x1c44, 0x1c45, 0x1c46, 0x1c47, 0x1c48,
-	0x1c49, 0x1c4a, 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, 0x1c4f, 0x1c50, 0x1c51,
-	0x1c52, 0x1c53, 0x1c54, 0x1c55, 0x1c56, 0x1c57, 0x1c58, 0x1c59, 0x1c5a,
-	0x1c5b, 0x1c5c, 0x1c5d, 0x1c5e, 0x1c5f,
-
-	0x1e41, 0x1e42, 0x1e43, 0x1e44, 0x1e45, 0x1e46, 0x1e47, 0x1e48, 0x1e49,
-	0x1e4a, 0x1e4b, 0x1e4c, 0x1e4d, 0x1e4e, 0x1e4f, 0x1e50, 0x1e51, 0x1e52,
-	0x1e53, 0x1e54, 0x1e55, 0x1e56, 0x1e57, 0x1e58, 0x1e59, 0x1e5a, 0x1e5b,
-	0x1e5c, 0x1e5d, 0x1e5e, 0x1e5f,
-
-	0 };
-
-static const struct pci_driver pch_lpc __pci_driver = {
-	.ops	 = &device_ops,
-	.vendor	 = PCI_VID_INTEL,
-	.devices = pci_device_ids,
-};