nsekar@codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29967
Change subject: qclib: Add qclib support ......................................................................
qclib: Add qclib support
Add qclib support to configure pmic, clocks, DDR
Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Signed-off-by: Nitheesh Sekar nsekar@codeaurora.org Signed-off-by: Sricharan R sricharan@codeaurora.org --- M src/mainboard/google/mistral/mainboard.c M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/include/soc/qclib.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/qclib_execute.c 8 files changed, 247 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29967/1
diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index 7201874..f4fc31e 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -18,12 +18,14 @@ #include <timestamp.h> #include <soc/usb.h>
+#if 0 static struct usb_board_data usb0_board_data = { .parameter_override_x0 = 0x63, .parameter_override_x1 = 0x03, .parameter_override_x0 = 0x1d, .parameter_override_x1 = 0x03, }; +#endif
static struct usb_board_data usb1_board_data = { .parameter_override_x0 = 0x63, @@ -35,7 +37,7 @@ static void setup_usb(void) { /* Setting Primarty usb controller */ - setup_usb_host(HSUSB_SS_PORT_0, &usb0_board_data); + //setup_usb_host(HSUSB_SS_PORT_0, &usb0_board_data);
/* Setting secondary usb controller */ setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data); diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 31e5113..e53f485 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -21,19 +21,18 @@ #include <timestamp.h> #include <arch/stages.h> #include <soc/usb.h> +#include <soc/qclib.h>
-#ifdef CONFIG_QC_SOC_SIMULATE extern void qcs405_mmu_dram_config_c(void); -#endif void platform_romstage_main(void) { + /* QCLib: DDR init & train */ + qclib_load_and_run(); + /* * Do DWC3 core and phy reset. Kick these resets off early * so they get atleast 1msec to settle. */ reset_usb(HSUSB_SS_PORT_0); reset_usb(HSUSB_HS_PORT_1); -#ifdef CONFIG_QC_SOC_SIMULATE - qcs405_mmu_dram_config_c(); -#endif } diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index c174cae..5e255e2 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -28,6 +28,7 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c romstage-y += usb.c +romstage-y += qclib_execute.c
################################################################################ ramstage-y += soc.c @@ -51,6 +52,28 @@ cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin
################################################################################ +QCLIB_FILE := $(QCS405_BLOB)/QcLib.elf +qclib_file := $(shell ls $(QCLIB_FILE)) +ifneq (,$(findstring $(QCLIB_FILE),$(qclib_file))) + QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib + $(QCLIB_CBFS)-file := $(QCLIB_FILE) + $(QCLIB_CBFS)-type := stage + $(QCLIB_CBFS)-compression := none + cbfs-files-y += $(QCLIB_CBFS) +endif + +################################################################################ +PMIC_FILE := $(QCS405_BLOB)/pmic.elf +pmic_file := $(shell ls $(PMIC_FILE)) +ifneq (,$(findstring $(PMIC_FILE),$(pmic_file))) + PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg + $(PMIC_CBFS)-file := $(PMIC_FILE) + $(PMIC_CBFS)-type := stage + $(PMIC_CBFS)-compression := none + cbfs-files-y += $(PMIC_CBFS) +endif + +################################################################################ QC_SEC_FILE := $(QCS405_BLOB)/qc_sec.mbn qc_sec_file := $(shell ls $(QC_SEC_FILE)) ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 03c6edb..dadbbe8 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -30,8 +30,8 @@ SSRAM_END(0x8608000)
BSRAM_START(0x8C00000) - OVERLAP_VERSTAGE_ROMSTAGE(0x8C00000, 100K) - REGION(fw_reserved2, 0x8C19000, 0x16000, 4096) + REGION(fw_reserved2, 0x8C00000, 0x16000, 4096) + OVERLAP_VERSTAGE_ROMSTAGE(0x8C16000, 100K) BOOTBLOCK(0x8C2F000, 40K) TTB(0x8C39000, 56K) VBOOT2_WORK(0x8C47000, 16K) @@ -39,10 +39,10 @@ TIMESTAMP(0x8C4F000, 1K) PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) PRERAM_CBFS_CACHE(0x8C57400, 70K) - REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100) -/* REGION(qclib, 0x8D0B000, 0x80000, 4096) - REGION(dcb, 0x8D8B000, 0x4000, 4096) - REGION(pmic, 0x8D8F000, 0xA000, 4096)*/ + //REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100) + REGION(qclib, 0x8C69000, 0x80000, 4096) + REGION(dcb, 0x8CE9000, 0x4000, 4096) + REGION(pmic, 0x8CED000, 0x10000, 4096) BSRAM_END(0x8D80000)
DRAM_START(0x80000000) diff --git a/src/soc/qualcomm/qcs405/include/soc/qclib.h b/src/soc/qualcomm/qcs405/include/soc/qclib.h new file mode 100644 index 0000000..b6a681e --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/qclib.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_QCS405_QCLIB_H__ +#define _SOC_QUALCOMM_QCS405_QCLIB_H__ + +#include <fmap.h> + +/* coreboot & QCLib I/F definitions */ + +/* TE_NAME (table entry name) */ +#define TE_NAME_LENGTH 24 /* length (bytes) of name field */ +#define TE_DDR_INFORMATION "ddr_information" +#define TE_DCB_SETTINGS "dcb_settings" +#define TE_PMIC_SETTINGS "pmic_settings" +#define TE_DDR_TRAINING_DATA "ddr_training_data" +#define TE_LIMITS_CFG_DATA "limits_cfg_data" +#define TE_QCLIB_LOG_BUFFER "qclib_log_buffer" + +#if IS_ENABLED(CONFIG_QC_SDI_ENABLE) +#define TE_QCSDI "qcsdi" +#endif + +/* TE_INDEX (table entry index) */ +/* te_index_ddr_information must be first index + This allows DDR mmu configuration to occcur first + in case other write operations require DDR access */ +enum te_index { + te_index_ddr_information, /* 00 */ + te_index_dcb, /* 01 */ + te_index_pmic, /* 02 */ + te_index_ddr_training, /* 03 */ + te_index_limits_cfg, /* 04 */ + te_index_qclib_log_buffer, /* 05 */ + + /* add new entries above */ +#if IS_ENABLED(CONFIG_QC_SDI_ENABLE) + te_index_qcsdi, /* ALWAYS LAST */ +#endif + te_index_last +}; + +/* BA_BMASK_VALUES (blob_attributes bit mask values) */ +#define BA_BMASK_SAVE_TO_STORAGE 0x00000001 + +struct qclib_cb_if_table_entry { + const char name[TE_NAME_LENGTH]; /* 0x00 TE_NAME */ + uint64_t blob_address; /* 0x18 blob addr in SRAM */ + uint32_t size; /* 0x20 blob size in SRAM */ + uint32_t blob_attributes; /* 0x24 BA_BMASK_VALUES */ +}; + +/* GA_BMASK_VALUES (global_attributes bit mask values) */ +#define GA_BMASK_ENABLE_SOC_DEBUG_FLOW 0x00000001 +#define GA_BMASK_ENABLE_UART_LOGGING 0x00000002 + +#define INTERFACE_VERSION 0x00000001 +#define MAX_NUMBER_OF_ENTRIES 16 + +#define QCLIB_MAGIC_NUMBER 0x51434C49425F4342 /* QCLIB_CB */ + +struct qclib_cb_if_table_header { + uint64_t magic; /* 0x00 */ + uint32_t version; /* 0x08 */ + uint32_t num_entries; /* 0x0C */ + uint32_t max_entries; /* 0x10 */ + uint32_t global_attributes; /* 0x14 */ + uint64_t reserved; /* 0x18 */ + struct qclib_cb_if_table_entry te[MAX_NUMBER_OF_ENTRIES]; /* 0x20 */ +}; + +/* fmap_region[] table index */ +enum fmap_region_index { + fmap_ddr_region, + fmap_limits_cfg, + fmap_region_max +}; + +/* Region Device for Data in Flash */ +struct fmap_region { + struct region_device dev; + size_t size; + bool dev_valid; + enum te_index index; + char fmap_name[TE_NAME_LENGTH]; +}; + +void qclib_load_and_run(void); + +#endif // _SOC_QUALCOMM_QCS405_QCLIB_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index f7cdc8d..447b7ae 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -30,4 +30,12 @@ extern u8 _edram_reserved[]; #define _dram_reserved_size (_edram_reserved - _dram_reserved)
+extern u8 _dcb[]; +extern u8 _edcb[]; +#define _dcb_size (_edcb - _dcb) + +extern u8 _pmic[]; +extern u8 _epmic[]; +#define _pmic_size (_epmic - _pmic) + #endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c index bebca24..ecae39f 100644 --- a/src/soc/qualcomm/qcs405/mmu.c +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -27,16 +27,12 @@ MA_DEV | MA_S | MA_RW); mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW); mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW); -#ifdef CONFIG_QC_SOC_SIMULATE mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_S | MA_RW); -#endif
mmu_enable(); }
-#ifdef CONFIG_QC_SOC_SIMULATE void qcs405_mmu_dram_config_c(void) { mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); } -#endif diff --git a/src/soc/qualcomm/qcs405/qclib_execute.c b/src/soc/qualcomm/qcs405/qclib_execute.c new file mode 100644 index 0000000..917a04c --- /dev/null +++ b/src/soc/qualcomm/qcs405/qclib_execute.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/cache.h> +#include <arch/mmu.h> +#include <cbfs.h> +#include <halt.h> +#include <console/console.h> +#include <timestamp.h> +#include <soc/mmu.h> +#include <soc/qclib.h> +#include <soc/symbols.h> + +#define PMIC_NAME "/pmiccfg" +#define DCB_NAME "/dcb" +#define QCLIB_NAME "/qclib" + +#define PBL_DATA_PTR 0x8c101a0 //0x14810188 + +void qclib_load_and_run(void) +{ + int (*doit)(void *, void *); + void *arg; + int ret_code; + struct mmu_context pre_qclib_mmu_context; + + struct prog qclib = + PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX QCLIB_NAME); + + struct prog pmic = + PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX PMIC_NAME); + + /* Attempt to load PMICCFG Blob */ +#if 0 + if (!cbfs_boot_load_file(CONFIG_CBFS_PREFIX PMIC_NAME, + _pmic, _pmic_size, CBFS_TYPE_RAW)) + goto fail; +#else + if (prog_locate(&pmic)) + goto fail; + + if (cbfs_prog_stage_load(&pmic)) + goto fail; +#endif + /* Attempt to load DCB Blob */ +// if (!cbfs_boot_load_file(CONFIG_CBFS_PREFIX DCB_NAME, +// _dcb, _dcb_size, CBFS_TYPE_RAW)) +// goto fail; + + /* Attempt to load QCLib elf */ + if (prog_locate(&qclib)) + goto fail; + + if (cbfs_prog_stage_load(&qclib)) + goto fail; + + prog_set_entry(&qclib, qclib.entry, (void *)PBL_DATA_PTR); + + printk(BIOS_DEBUG, "\n\n\nQCLib is about to Initialize PMIC and DDR\n"); + printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n", + prog_entry(&qclib), prog_entry_arg(&qclib)); + + doit = prog_entry(&qclib); + arg = prog_entry_arg(&qclib); + + /* back-up mmu context before disabling mmu and executing qclib */ + mmu_save_context(&pre_qclib_mmu_context); + /* disable mmu before jumping to qclib. mmu_disable also + flushes and invalidates caches before disabling mmu. */ + mmu_disable(); + + ret_code = doit(arg, NULL); + printk(BIOS_DEBUG, "QCLib completed\n\n\n"); + + /* Before returning, QCLib flushes cache and disables mmu. + Explicitly disable mmu (flush, invalidate and disable mmu) + before re-enabling mmu with backed-up mmu context */ + mmu_disable(); + mmu_restore_context(&pre_qclib_mmu_context); + mmu_enable(); + + qcs405_mmu_dram_config_c(); + return; + +fail: + die("Couldn't run QCLib.\n"); +} +
-
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