Change in coreboot[master]: WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps

[Nikolai Vyssotski (Code Review)]

Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45278 )

Change subject: WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps
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WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps

Use GPIOs mapping defined in APCB GET_SPD_FROM_GPIO to fetch correct SPD
block from PSP BIOS table entry type 0x69 (BIOS_SPD_DATA). There is
only one APCB now with no SPD data in it. No need for board ID getting
method. This will save ROM space consumed by multiple APCB copies
in the past.

This is a working example of an implementation tested on Dalboz. It does
not require patching with APCB_EDIT_TOOL. All SPDs are assembled in one
type 0x69 blob and inserted into PSP BIOS directory.

BUG=b:127505025
TEST=Dalboz with CABLRV20090300 and test CB and boot loader code
BRANCH=Zork

Change-Id: I9adf7a016ee481214b47d8adc6d53fd8ce0c9bd4
Signed-off-by: Nikolai Vyssotski 
---
M src/soc/amd/picasso/Makefile.inc
M util/amdfwtool/amdfwtool.c
2 files changed, 42 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45278/1

diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index eb2be50..e83e08d 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -198,7 +198,7 @@
 #

# type = 0x60
-PSP_APCB_FILES=$(APCB_SOURCES)
+PSP_SPD_FILES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/SPD_$(f).bin)

# type = 0x61
 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
@@ -262,6 +262,12 @@
 # type = 0xb - See #55758 (NDA) for bit definitions.
 PSP_SOFTFUSE_BITS += 28

+# SPD data array blob (with SPDs for all possible memory IDs for this platform)
+SPD_BLOB:=$(obj)/SPD_array.bin
+
+# APCB binary without SPD data
+APCB_NO_SPD_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin
+
 # Helper function to return a value with given bit set
 set-bit=$(call int-shift-left, 1 $(call _toint,$1))
 PSP_SOFTFUSE=$(shell A=$(call int-add, \
@@ -304,9 +310,8 @@
 OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage)
 OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig)

-OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \
-	$(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \
-	--instance $(shell printf "%x" $$(($(i)-1))) --apcb ))
+OPT_PSP_APCB_FILE=$(call add_opt_prefix,  $(APCB_NO_SPD_BLOB), --instance 0 --apcb)
+OPT_SPD_BLOB=$(call add_opt_prefix, $(SPD_BLOB), --spd-data-blob)

OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base)
 OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
@@ -341,7 +346,8 @@
    	$(OPT_SMUFW2_SUB2_FILE) \
    	$(OPT_SMUFW1_SUB1_FILE) \
    	$(OPT_SMUFW2_SUB1_FILE) \
-		$(OPT_PSP_APCB_FILES) \
+		$(OPT_PSP_APCB_FILE) \
+		$(OPT_SPD_BLOB) \
    	$(OPT_APOB_ADDR) \
    	$(OPT_PSP_BIOSBIN_FILE) \
    	$(OPT_PSP_BIOSBIN_DEST) \
@@ -383,6 +389,16 @@
    	--soc-name "Picasso" \
    	--flashsize $(CONFIG_ROM_SIZE)

+# Copy prebuild APCBs if they exist
+$(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin
+	cp $< $@
+
+$(obj)/SPD_%.bin:	$$(SPD_SOURCES_DIR)/%.hex
+	xxd -r -p $< > $@
+
+$(SPD_BLOB):	$$(PSP_SPD_FILES)
+	cat $+ > $@
+
 $(obj)/amdfw.rom:	$(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \
    		$(call strip_quotes, $(PSPBTLDR_FILE)) \
    		$(call strip_quotes, $(PSPSCUREOS_FILE)) \
@@ -418,12 +434,22 @@
    		$(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \
    		$(PSP_VERSTAGE_FILE) \
    		$(PSP_VERSTAGE_SIG_FILE) \
-			$$(PSP_APCB_FILES) \
+			$(PSP_APCB_FILE) \
+			$(SPD_BLOB) \
    		$(AMDFWTOOL) \
    		$(obj)/fmap.fmd
    $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
    rm -f $@
    @printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
+	echo $(AMDFWTOOL) \
+		$(OPT_PSPBTLDR_FILE) \
+		$(AMDFW_COMMON_ARGS) \
+		$(OPT_APOB0_NV_SIZE) \
+		$(OPT_APOB0_NV_BASE) \
+		$(OPT_VERSTAGE_FILE) \
+		$(OPT_VERSTAGE_SIG_FILE) \
+		--location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \
+		--output $@
    $(AMDFWTOOL) \
    	$(OPT_PSPBTLDR_FILE) \
    	$(AMDFW_COMMON_ARGS) \
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index f385068..2192a04 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -215,6 +215,7 @@
    printf("-q | --anywhere                Use any 64-byte aligned addr for Directory\n");
    printf("-R | --sharedmem               Location of PSP/FW shared memory\n");
    printf("-P | --sharedmem-size          Maximum size of the PSP/FW shared memory area\n");
+	printf("--spd-data-blob		       Add SPD array\n");
    printf("-C | --soc-name <socname>      Specify SOC name. Supported names are\n");
    printf("                               Stoneyridge, Raven, Picasso, Renoir or Lucienne");
    printf("-h | --help                    show this help\n");
@@ -251,6 +252,7 @@
    AMD_BIOS_PMUD = 0x65,
    AMD_BIOS_UCODE = 0x66,
    AMD_BIOS_APCB_BK = 0x68,
+	AMD_BIOS_SPD_DATA = 0x69,
    AMD_BIOS_MP2_CFG = 0x6a,
    AMD_BIOS_PSP_SHARED_MEM = 0x6b,
    AMD_BIOS_L2_PTR =  0x70,
@@ -409,6 +411,7 @@
    { .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH },
    { .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH },
    { .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH },
+	{ .type = AMD_BIOS_SPD_DATA, .inst = 0, .level = BDT_BOTH },
    { .type = AMD_BIOS_APOB, .level = BDT_BOTH },
    { .type = AMD_BIOS_BIN,
    		.reset = 1, .copy = 1, .zlib = 1, .level = BDT_BOTH },
@@ -1085,6 +1088,7 @@
    LONGOPT_SPI_READ_MODE	= 256,
    LONGOPT_SPI_SPEED	= 257,
    LONGOPT_SPI_MICRON_FLAG	= 258,
+	LONGOPT_SPD_DATA	= 259,
 };

// Unused values: D
@@ -1136,6 +1140,7 @@
    {"mp2-config",       required_argument, 0, 'X' },
    {"apob-nv-base",     required_argument, 0, 'F' },
    {"apob-nv-size",     required_argument, 0, 'H' },
+	{"spd-data-blob",    required_argument, 0, LONGOPT_SPD_DATA },
    /* Embedded Firmware Structure items*/
    {"spi-read-mode",    required_argument, 0, LONGOPT_SPI_READ_MODE },
    {"spi-speed",        required_argument, 0, LONGOPT_SPI_SPEED },
@@ -1450,6 +1455,11 @@
    						instance, optarg);
    		sub = instance = 0;
    		break;
+		case LONGOPT_SPD_DATA:
+			/* optional SPD data array outside of APCB */
+			register_bdt_data(AMD_BIOS_SPD_DATA, sub, instance, optarg);
+			sub = instance = 0;
+			break;
    	case 'Q':
    		/* APOB destination */
    		register_fw_addr(AMD_BIOS_APOB, 0, optarg, 0);