Change in coreboot[master]: soc/intel/tigerlake: update elog to include CSME reset causes

[Derek Huang (Code Review)]

Derek Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41026 )

Change subject: soc/intel/tigerlake: update elog to include CSME reset causes
......................................................................

soc/intel/tigerlake: update elog to include CSME reset causes

Call out the CSME-initiated bits from HPR_CAUSE0 register and
update the elog to include reset causes

Change-Id: I32ffb55ff2ad26ec4e7609c41fc65e021a327a14
Signed-off-by: derek.huang 
---
M src/soc/intel/tigerlake/elog.c
1 file changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/41026/1

diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c
index 2aceea0..5b6c9db 100644
--- a/src/soc/intel/tigerlake/elog.c
+++ b/src/soc/intel/tigerlake/elog.c
@@ -62,6 +62,18 @@
    if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
    	elog_add_event(ELOG_TYPE_THERM_TRIP);

+	/* CSME-Initiated Host Reset with power down */
+	if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPD)
+		elog_add_event(ELOG_TYPE_MI_HRPD);
+
+	/* CSME-Initiated Host Reset with power cycle */
+	if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPC)
+		elog_add_event(ELOG_TYPE_MI_HRPC);
+
+	/* CSME-Initiated Host Reset without power cycle */
+	if (ps->hpr_cause0 & HPR_CAUSE0_MI_HR)
+		elog_add_event(ELOG_TYPE_MI_HR);
+
    /* PWR_FLR Power Failure */
    if (ps->gen_pmcon_a & PWR_FLR)
    	elog_add_event(ELOG_TYPE_POWER_FAIL);

[Alex Levin (Code Review)]

Alex Levin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41026 )

Change subject: soc/intel/tigerlake: update elog to include CSME reset causes
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41026/1/src/soc/intel/tigerlake/elo... 
File src/soc/intel/tigerlake/elog.c:

https://review.coreboot.org/c/coreboot/+/41026/1/src/soc/intel/tigerlake/elo... 
PS1, Line 66: ps->hpr_cause0
is there a reason not to log the entire cause register?

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41026 )

Change subject: soc/intel/tigerlake: update elog to include CSME reset causes
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41026/1/src/soc/intel/tigerlake/elo... 
File src/soc/intel/tigerlake/elog.c:

https://review.coreboot.org/c/coreboot/+/41026/1/src/soc/intel/tigerlake/elo... 
PS1, Line 66: ps->hpr_cause0
> is there a reason not to log the entire cause register?

The others are far less interesting... they include SMBUS or eSPI slaves causing a reset, SYS_RESET# 0xCF9 writes, and the TCO watchdog expiring the 2nd time. I imagine it will be useful for helping to debug CB:35403 and friends once we've gotten further along with that functionality.

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41026 )

Change subject: soc/intel/tigerlake: update elog to include CSME reset causes
......................................................................

Patch Set 1: Code-Review+2

[Nick Vaccaro (Code Review)]

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41026 )

Change subject: soc/intel/tigerlake: update elog to include CSME reset causes
......................................................................

Patch Set 1: Code-Review+2

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41026 )

Change subject: soc/intel/tigerlake: update elog to include CSME reset causes
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41026/1/src/soc/intel/tigerlake/elo... 
File src/soc/intel/tigerlake/elog.c:

https://review.coreboot.org/c/coreboot/+/41026/1/src/soc/intel/tigerlake/elo... 
PS1, Line 66: ps->hpr_cause0
> The others are far less interesting... […]

Ack

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41026 )

Change subject: soc/intel/tigerlake: update elog to include CSME reset causes
......................................................................

soc/intel/tigerlake: update elog to include CSME reset causes

Call out the CSME-initiated bits from HPR_CAUSE0 register and
update the elog to include reset causes

Change-Id: I32ffb55ff2ad26ec4e7609c41fc65e021a327a14
Signed-off-by: derek.huang 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41026
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Nick Vaccaro 
---
M src/soc/intel/tigerlake/elog.c
1 file changed, 12 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c
index 586dbfd..d5b8754 100644
--- a/src/soc/intel/tigerlake/elog.c
+++ b/src/soc/intel/tigerlake/elog.c
@@ -61,6 +61,18 @@
    if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
    	elog_add_event(ELOG_TYPE_THERM_TRIP);

+	/* CSME-Initiated Host Reset with power down */
+	if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPD)
+		elog_add_event(ELOG_TYPE_MI_HRPD);
+
+	/* CSME-Initiated Host Reset with power cycle */
+	if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPC)
+		elog_add_event(ELOG_TYPE_MI_HRPC);
+
+	/* CSME-Initiated Host Reset without power cycle */
+	if (ps->hpr_cause0 & HPR_CAUSE0_MI_HR)
+		elog_add_event(ELOG_TYPE_MI_HR);
+
    /* PWR_FLR Power Failure */
    if (ps->gen_pmcon_a & PWR_FLR)
    	elog_add_event(ELOG_TYPE_POWER_FAIL);

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41026 )

Change subject: soc/intel/tigerlake: update elog to include CSME reset causes
......................................................................

Patch Set 2:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4718
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4717
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4716
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4715

Please note: This test is under development and might not be accurate at all!