Patch set updated for coreboot: Strago: Enable CA Mirror

[Hannah Williams]

Hannah Williams ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12749

-gerrit

commit bdbb2b7f628c899ebc5986394cf9ad3055744a01
Author: Shobhit Srivastava 
Date:   Fri Oct 9 17:05:16 2015 +0530

Strago: Enable CA Mirror

Configuring UPD PcdCaMirrorEn. This is a board specific parameter.
    CA mirror is the Command Address mirroring option that is enabled
    on this board

CQ-DEPEND=CL:13038

Original-Reviewed-on: https://chromium-review.googlesource.com/309190
    Original-Reviewed-by: Aaron Durbin 
    Original-Tested-by: Hannah Williams 
    Original-Reviewed-by: Duncan Laurie

Change-Id: I05174e18d650332d838e5036c713e91c4840ee75
    Signed-off-by: Divya Sasidharan 
    Signed-off-by: Hannah Williams 
---
 src/mainboard/intel/strago/devicetree.cb   | 1 +
 src/soc/intel/braswell/chip.h              | 1 +
 src/soc/intel/braswell/romstage/romstage.c | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb
index 3b93f44..ae8c11e 100755
--- a/src/mainboard/intel/strago/devicetree.cb
+++ b/src/mainboard/intel/strago/devicetree.cb
@@ -13,6 +13,7 @@ chip soc/intel/braswell
    register "PcdApertureSize" = "2"
    register "PcdGttSize" = "1"
    register "PcdDvfsEnable" = "0"
+	register "PcdCaMirrorEn" = "1"

############################################################
    # Set the parameters for SiliconInit
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 7b01f0b..e302d6c 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -75,6 +75,7 @@ struct soc_intel_braswell_config {
    UINT8  PcdGttSize;
    UINT8  PcdLegacySegDecode;
    UINT8  PcdDvfsEnable;
+	UINT8  PcdCaMirrorEn; /* Command Address Mirroring Enabled */

/*
     * The following fields come from fsp_vpd.h .aka. VpdHeader.h.
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 71402ac..5c38c18 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -219,6 +219,7 @@ void soc_memory_init_params(struct romstage_params *params,
    upd->PcdGttSize = config->PcdGttSize;
    upd->PcdLegacySegDecode = config->PcdLegacySegDecode;
    upd->PcdDvfsEnable = config->PcdDvfsEnable;
+	upd->PcdCaMirrorEn = config->PcdCaMirrorEn;
 }

void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,